Data security method and device for computer modules

Abstract

A security method for an attached computer module in a computer system. The security method reads a security identification number in an attached computer module and compares it to a security identification number in a console, which houses the attached computer module. Based upon a relationship between these numbers, a security status is selected. The security status determines the security level of operating the computer system.

What is claimed is: 
     
       1. A security protection method for a computer module, said method comprising:
 inserting the computer module into a console;   initiating a security program in said module to read a security identification of said console and to read a security identification of said computer module;   determining of a predetermined security status based upon a relationship of said console identification and said computer module identification;   selecting said predetermined security status; and   operating said computer module based upon said security status.   
     
     
       2. The method of  claim 1  wherein said predetermined security status disables a network access to the computer module. 
     
     
       3. The method of  claim 1  wherein said predetermined security status disables a secondary storage of information from said computer module to substantially prevent information to be transferred from a memory of the computer module to said secondary storage. 
     
     
       4. The method of  claim 1  wherein said security program is provided in a system BIOS. 
     
     
       5. The method of  claim 1  wherein said step of initiating reads said security identification of said computer module from a flash memory device. 
     
     
       6. The method of  claim 1  wherein said step of initiating reads said security identification of said console from a flash memory device. 
     
     
       7. The method of  claim 1  wherein said console is selected from a desktop home computing device, an office desktop computing device, a mobile computing device, a television sot-top computing device, and a co-worker's computing device. 
     
     
       8. A system for secured information transactions, the system comprising:
 a console comprising a peripheral controller housed in the console;   a user identification input device coupled to the peripheral controller, the user identification input device being provided for user identification data; and   an attached computer module coupled to the console, the attached computer module comprising a security memory device stored with the user identification data.   
     
     
       9. The system of  claim 8  wherein the user identification input device is a finger print reader. 
     
     
       10. The system of  claim 8  wherein the user identification input device is a voice processing device. 
     
     
       11. A method for operating a module computer into one of a plurality of network systems, the method comprising:
 providing a computer module, the module comprising a connection program;   inserting the computer module into a computer console, the computer console having access to a network;   receiving connection information from the computer console;   configuring the connection program to adapt to the connection information; and   establish a connection between the computer module and a server coupled to the network.   
     
     
       12. The method of  claim 11  wherein the connection information comprises a connection protocol for providing the connection. 
     
     
       13. The method of  claim 12  wherein the connection protocol is selected from TCP/IP, or mobile IP. 
     
     
       14. A computer for information transactions, comprising:
 a central processing unit directly connected to a first Low Voltage Differential Signal (LVDS) channel comprising two sets of unidirectional, serial bit channels to transmit data in opposite directions;   a main memory directly connected to the central processing unit; and   a peripheral bridge directly coupled to the central processing unit without any intervening Peripheral Component Interconnect (“PCI”) bus, wherein the peripheral bridge directly conveys an encoded serial bit stream of address and data bits of a PCI bus transaction over a second LVDS channel comprising two sets of unidirectional, serial bit channels to transmit data in opposite directions.   
     
     
       15. The computer of claim 14, further comprising a connector coupled to a console, wherein the second LVDS channel communicates the encoded serial bit stream of address and data bits of the PCI bus transaction to the console. 
     
     
       16. The computer of claim 15 further comprising a graphics controller that conveys digital video display information from the connector to the console. 
     
     
       17. The computer of claim 15 wherein the console comprises a mass storage device that couples to the second LVDS channel. 
     
     
       18. A computer system, comprising:
 a console comprising a Liquid Crystal Display (LCD) display and a first Low Voltage Differential Signal (LVDS) channel comprising two sets of unidirectional, serial bit channels to transmit data in opposite directions; and   a computer coupled to the console through a connector, the computer comprising
 an integrated central processing unit and graphics controller in a single chip directly connected to a second LVDS channel comprising two sets of unidirectional, serial bit channels to transmit data in opposite directions; and 
 a mass storage unit coupled to the central processing unit and graphics controller in a single chip; 
 wherein the graphics controller conveys digital video display information to the LCD display through the connector upon coupling to the console. 
   
     
     
       19. The computer system of claim 18 wherein the computer further comprises a peripheral bridge directly coupled to the central processing unit without any intervening Peripheral Component Interconnect (“PCI”) bus, the peripheral bridge directly conveying an encoded serial bit stream of address and data bits of a PCI bus transaction. 
     
     
       20. The computer system of claim 19 wherein the peripheral bridge conveys the encoded serial bit stream of address and data bits of the PCI bus transaction to the first LVDS channel upon coupling of the computer to the console. 
     
     
       21. A computer, comprising:
 a central processing unit directly connected to a first Low Voltage Differential Signal (LVDS) channel comprising two sets of unidirectional, serial bit channels to transmit Universal Serial Bus (USB) Protocol data in opposite directions;   a second LVDS channel comprising two sets of unidirectional, serial bit channels to transmit data in opposite directions;   a connector coupled to the first LVDS channel; and   a main memory directly coupled to the central processing unit.   
     
     
       22. The computer of claim 21 wherein the second LVDS channel communicates an encoded serial bit stream of address and data bits of a Peripheral Component Interconnect (“PCI”) bus transaction. 
     
     
       23. The computer of claim 21 wherein the first LVDS channel conveys Universal Serial Bus (USB) Protocol data to a console through the connector. 
     
     
       24. A computer, comprising:
 an integrated central processing unit and graphics controller in a single chip directly connected to a Low Voltage Differential Signal (LVDS) channel comprising two sets of unidirectional, serial bit channels to transmit data in opposite directions;   a main memory directly coupled to the integrated central processing unit and graphics controller;   a differential signal channel directly extending from the integrated central processing unit and graphics controller to convey digital video display information;   a connector for coupling to a console; and   a second differential signal channel comprising two sets of unidirectional, serial bit channels to transmit data in opposite directions, wherein the second differential signal channel conveys Universal Serial Bus (USB) protocol data through the connector to the console.   
     
     
       25. The computer of claim 24 wherein the LVDS channel conveys an encoded serial bit stream of address and data bits of a Peripheral Component Interconnect (“PCI”) bus transaction. 
     
     
       26. A modular computer system, comprising:
 a console comprising a first Low Voltage Differential Signal (LVDS) channel comprising two sets of unidirectional, serial bit channels to transmit data in opposite directions; and   a computer coupled to the console through a connector, the computer comprising
 a central processing unit, 
 a mass storage unit coupled to the central processing unit, 
 a second LVDS channel comprising two sets of unidirectional, serial bit channels to transmit data in opposite directions, and 
 a peripheral bridge directly coupled to the central processing unit without any intervening Peripheral Component Interconnect bus, wherein the peripheral bridge directly conveys an encoded serial bit stream of address and data bits of a Peripheral Component Interconnect (“PCI”) bus transaction over the second LVDS channel; and 
 wherein the second LVDS channel communicates to the first LVDS channel in the console upon the computer coupling to the console. 
   
     
     
       27. The modular computer system of claim 26 wherein the second LVDS channel conveys the encoded serial bit stream of the PCI bus transaction to the first LVDS channel upon coupling of the computer module to the console. 
     
     
       28. The modular computer system of claim 27 wherein the console further comprises a mass storage device that couples to the first and second LVDS channels. 
     
     
       29. A modular computer system, comprising:
 a console comprising a power supply; and   a computer coupled to the console through a connector, the computer comprising
 a central processing unit, 
 a first Low Voltage Differential Signal (LVDS) channel comprising two sets of unidirectional, multiple serial bit channels to transmit data in opposite directions, 
 a peripheral bridge directly coupled to the first LVDS channel to communicate an encoded serial bit stream of address and data bits of a Peripheral Component Interconnect (“PCI”) bus transaction, the peripheral bridge directly coupled to the central processing unit without any intervening PCI bus, and 
   wherein the power supply supplies power to the computer upon coupling to the console.   
     
     
       30. The computer system of claim 29 further comprising a second LVDS channel that conveys the encoded serial bit stream of address and data bits of the PCI bus transaction, wherein the second LVDS channel directly extends from the central processing unit. 
     
     
       31. A modular computer system, comprising:
 a console comprising a first Low Voltage Differential Signal (LVDS) channel comprising two sets of unidirectional, serial bit channels to transmit data in opposite directions; and   a computer that couples to the console, the computer comprising
 an integrated central processing unit and graphics controller in a single chip, directly connected to a second LVDS channel comprising two sets of unidirectional, serial bit channels to transmit data in opposite directions, and 
 a connector that couples to the first LVDS channel in the console. 
   
     
     
       32. The modular computer system of claim 31 wherein the second LVDS channel conveys an encoded serial bit stream of address and data bits of a Peripheral Component Interconnect (“PCI”) bus transaction. 
     
     
       33. The modular computer system of claim 31 wherein the first LVDS channel conveys an encoded serial bit stream of address and data bits of a Peripheral Component Interconnect (“PCI”) bus transaction. 
     
     
       34. The modular computer system of claim 31 wherein the computer conveys Universal Serial Bus (USB) protocol data to the console upon the computer coupling to the console. 
     
     
       35. A computer, comprising:
 a central processing unit;   a main memory directly connected to the central processing unit;   a peripheral bridge directly coupled to the central processing unit without any intervening Peripheral Component Interconnect (PCI) bus, wherein the peripheral bridge directly conveys an encoded serial bit stream of address and data bits of a Peripheral Component Interconnect (PCI) bus transaction over a first Low Voltage Differential Signal (LVDS) channel comprising two sets of unidirectional, serial bit channels to transmit data in opposite directions; and   a mass storage device directly coupled the peripheral bridge.   
     
     
       36. The computer of claim 35 further comprising a graphics controller coupled to the peripheral bridge. 
     
     
       37. A computer, comprising:
 a central processing unit directly connected to a first Low Voltage Differential Signal (LVDS) channel to convey a first encoded serial bit stream of address and data bits of a Peripheral Component Interconnect (PCI) bus transaction;   a main memory directly connected to the central processing unit; and   a peripheral bridge directly coupled to the central processing unit without any intervening PCI bus, wherein the peripheral bridge directly conveys a second encoded serial bit stream of address and data bits of a (PCI) bus transaction over a second LVDS channel comprising two sets of unidirectional, serial bit channels to transmit data in opposite directions.   
     
     
       38. The computer of claim 37 further comprising a connector coupled to a console, wherein the second LVDS channel communicates the second encoded serial bit stream of address and data bits of the PCI bus transaction to the console. 
     
     
       39. The computer of claim 38 further comprising a graphics controller to convey digital video display information from the connector to the console. 
     
     
       40. The computer of claim 38 wherein the console comprises a peripheral device that couples to the second LVDS channel. 
     
     
       41. A computer, comprising:
 an integrated central processing unit and graphics controller in a single chip directly connected to a first Low Voltage Differential Signal (LVDS) channel comprising two sets of unidirectional, serial bit channels to transmit data in opposite directions, wherein the integrated central processing unit and graphics controller conveys digital video display signals through a second differential signal channel;   a main memory directly coupled to the integrated central processing unit and graphics controller; and   a mass storage device comprising flash memory.   
     
     
       42. The computer of claim 41 wherein the second differential signal channel conveys Transition Minimized Differential Signaling (TDMS) information. 
     
     
       43. The computer of claim 41 wherein the first LVDS channel conveys an encoded serial bit stream of address and data bits of a Peripheral Component Interconnect (PCI) bus transaction. 
     
     
       44. A computer, comprising:
 an integrated central processing unit and graphics controller in a single chip directly connected to a first Low Voltage Differential Signal (LVDS) channel comprising two sets of unidirectional, serial bit channels to transmit data in opposite directions;   a main memory directly coupled to the integrated central processing unit and graphics controller;   a mass storage device comprising flash memory;   a connector that conveys Universal Serial Bus (USB) protocol information to a console; and   a second LVDS channel comprising two sets of unidirectional, serial bit channels to transmit data in opposite directions, wherein the second LVDS channel conveys said USB protocol information to the console through the connector.   
     
     
       45. A computer, comprising:
 a Central Processing Unit (CPU) directly connected to a Low Voltage Differential Signal (LVDS) channel comprising two sets of multiple, unidirectional, serial bit channels to convey an encoded serial bit stream of encoded address and data bits of a Peripheral Component Interconnect (“PCI”) bus transaction in opposite directions;   a main memory directly connected to the CPU; and   a mass storage device coupled to the CPU.   
     
     
       46. The computer of claim 45 further comprising a connector, wherein the connector connects to a console comprising a power supply, and the power supply supplies power to the computer upon coupling to the console. 
     
     
       47. The computer of claim 45 wherein the mass storage device comprises flash memory. 
     
     
       48. A computer, comprising:
 an integrated central processing unit and graphics controller in a single chip directly connected to a first Low Voltage Differential Signal (LVDS) channel comprising two sets of multiple, unidirectional, serial bit channels to convey an encoded serial bit stream of encoded address and data bits of a Peripheral Component Interconnect (PCI) bus transaction in opposite directions;   a main memory directly coupled to the integrated central processing unit and graphics controller; and   an Ethernet communication device coupled to the first LVDS channel.   
     
     
       49. The computer of claim 48 further comprising a connector, wherein the connector connects to a console comprising a power supply, and the power supply supplies power to the computer upon coupling to the console.