Device and method for repeatedly updating the function of a LCD monitor

Abstract

A monitor control system capable of reprogramming the function of a LCD monitor. The monitor control system utilizes VGA signal lines for video signal transmission during normal mode of operation and the same VGA signal lines for transmitting erase/record commands and data when the erasable programmable ROM inside the monitor demands reprogramming. Using an isolator circuit in the monitor control system for isolating an erase/record pathway of an erasable programmable ROM from a normal video pathway, data within the erasable programmable ROM can be modified without opening up the monitor casing. Hence, the modification of monitor function is much more convenient.

What is claimed is: 
     
       1. A device for reprogramming the function of a liquid crystal display (LCD) monitor, comprising:
 a set of video graphic adapter (VGA) signal lines for transmitting a plurality of erase/record commands and a plurality of erase/record data;   a signal detector coupled to the VGA signal lines for detecting and re-transmitting the erase/record commands and data;   an activation device coupled to the signal detector, wherein the activation device is normally connected to a video pathway, but as soon as erase/record commands are detected, the activation device is switched to an erase/record pathway so that erase/record commands and data can be re-directed;   a read-only-memory (ROM) erase/record command decoder connected to the activation device via the erase/record pathway, wherein the decoder translates the erase/record commands into a plurality of control signals and translates the erase/record data into a plurality of address signals and a plurality of data signals;   a plurality of signal lines for transferring the control signals, the address signals, and the data signals to an external ROM unit, wherein a content of the ROM unit can be modified according to the control signals, the address signals, and the data signals; and   a mode return device coupled to the ROM erase/record command decoder and the activation device, wherein the reprogramming status of the ROM unit can be determined from the address, data and read/write signals so that the activation device can be triggered to switch over connection from the erase/record pathway to the video pathway as soon as reprogramming is finished.   
     
     
       2. The device of  claim 1 , wherein the erase/record commands and data come from an erase/record device that couples to the VGA signal lines. 
     
     
       3. The device of  claim 2 , wherein the erase/record device is a computer platform that sends the erase/record commands and data in an inter-integrated circuit interface format via a parallel port VGA adapter. 
     
     
       4. The device of  claim 2 , wherein the erase/record device is an inter-integrated circuit interface circuit platform for transmitting erase/record commands and data in an inter-integrated circuit interface format. 
     
     
       5. The device of  claim 1 , wherein the signal detector further includes:
 an inter-integrated circuit multiple address content comparator circuit coupled to the VGA signal lines for comparing with a plurality of consecutive address sequences in the erase/record data such that a set signal is transmitted when there is a match with a pre-set address sequence; and   a monitor-in-system programming control flag unit coupled to the inter-integrated circuit multiple address content comparator circuit for transmitting a start signal after receiving the set signal.   
     
     
       6. The device of  claim 1 , wherein the activation device further includes:
 a monitor-in-system reprogramming initialization circuit for producing a select signal after receiving the start signal; and   an erase/record pathway isolator for switching over connection from the video pathway to the erase/record pathway after receiving the select signal and transmitting the erase/record commands and data via the erase/record pathway.   
     
     
       7. The device of  claim 1 , wherein the ROM erase/record command decoder further includes:
 an inter-integrated interface circuit for receiving and translating the erase/record commands and data; and   an erase/record command decoder for receiving translated erase/record commands and data and outputting address, data and erase/read/write signals.   
     
     
       8. The device of  claim 7 , wherein the erase/record command decoder further includes:
 a hidden ROM for holding a program code for erase/record commands;   a random access memory (RAM) unit for holding erase/record data;   a central processing unit coupled to the hidden ROM, the RAM unit and the inter-integrated interface circuit, wherein the central processing unit receives the erase/record commands and data passing through the inter-integrated circuit interface circuit and then stores the erase/record data in the RAM unit, while the erase/record commands are decoded by referring to the program code in the hidden ROM and then the decoded commands are re-transmitted; and   an erase/record control register coupled to the central processing unit for receiving the decoded erase/record commands and converting the erase/record commands into the interface control signals or erase/read/write signals, and converting the erase/record data stored in the RAM unit into address and data signals.   
     
     
       9. The device of  claim 7 , wherein the erase/record command decoder is a hardware circuit that separates each erase/record command picked up by the inter-integrated circuit into a plurality of states for ease of decoding and converts the erase/record commands and data into erase/read/write, address and data signals. 
     
     
       10. The device of  claim 1 , wherein the mode return device further includes:
 a mode return control register for receiving the address, data and erase/read/write signals and producing a mode return signal as soon as a reprogramming operation is finished; and   a mode return circuit coupled to the mode return control register and the activation device for sending a stop signal to the activation device after receiving the mode return signal so that the activation device switches over connection from the erase/record pathway back to the video pathway.   
     
     
       11. The device of  claim 1 , wherein the external ROM unit comprises a flash ROM unit. 
     
     
       12. The device of  claim 1 , wherein the external ROM unit comprises an erasable programmable ROM unit. 
     
     
       13. A system for reprogramming the function of a liquid crystal display (LCD) monitor, comprising:
 an erase/record device for holding and transmitting a plurality of erase/record commands and a plurality of erase/record data;   a set of video graphic adapter (VGA) signal lines coupled to the erase/record device for transmitting the erase/record commands and data; and   a LCD monitor controller with a monitor-in-system programming function, wherein the LCD monitor controller is coupled to the VGA signal lines so that the erase/record commands of the erase/record device and data are received from the erase/record device via the VGA signal lines, and then a plurality of address signals, a plurality of data signals, and a plurality of control signals are exported for reprogramming a ROM unit, wherein   the ROM unit coupled to the LCD monitor controller via signal lines for transferring the address signals, the data signals and the control signals, so that data stored in the ROM unit can be modified according to the address signals and the control signals, and the data signals coming from the LCD monitor controller.   
     
     
       14. The system of  claim 13 , wherein the erase/record device is a computer platform that sends the erase/record commands and data in an inter-integrated circuit interface format via a parallel port VGA adapter. 
     
     
       15. The system of  claim 13 , wherein the erase/record device is an inter-integrated circuit interface circuit platform for transmitting erase/record commands and data in an inter-integrated circuit interface format. 
     
     
       16. The system of  claim 13 , wherein the LCD monitor controller with monitor-in-system programming function includes:
 a signal detector coupled to the VGA signal lines for detecting and transmitting the erase/record commands and data;   an activation device coupled to the signal detector, wherein the activation device is normally connected to a video pathway, but as soon as erase/record commands is detected, the activation device is switched to an erase/record pathway so that erase/record commands and data can be re-directed;   a ROM erase/record command decoder connected to the activation device via the erase/record pathway, wherein the decoder translates the erase/record commands into a plurality of erase/read/write signals and translates the erase/record data into a plurality of address signals and a plurality of data signals; and   a mode return device coupled to the ROM record command decoder and the activation device, wherein the reprogramming status of a ROM unit can be determined from the address, data and erase/read/write signals so that the activation device can be triggered to switch over connection from the erase/record pathway to the video pathway as soon as reprogramming is finished.   
     
     
       17. The system of  claim 16 , wherein the signal detector further includes:
 an inter-integrated circuit multiple address content comparator circuit coupled to the VGA signal lines for comparing with a plurality of consecutive address sequences in the erase/record data such that a set signal is transmitted when there is a match with a pre-set address sequence; and   a monitor-in-system programming control flag unit coupled to the inter-integrated circuit multiple address content comparator circuit for transmitting a start signal after receiving the set signal.   
     
     
       18. The system of  claim 16 , wherein the activation device further includes:
 a monitor-in-system reprogramming initialization circuit for producing a select signal after receiving the start signal; and   an erase/record pathway isolator for switching over connection from the video pathway to the erase/record pathway after receiving the select signal and transmitting the erase/record commands and data via the erase/record pathway.   
     
     
       19. The system of  claim 16 , wherein the ROM erase/record command decoder further includes:
 an inter-integrated interface circuit for receiving and translating the erase/record commands and data; and   an erase/record command decoder for receiving translated erase/record commands and data and outputting address, data and erase/read/write signals.   
     
     
       20. The system of  claim 19 , wherein the erase/record command decoder further includes:
 a hidden ROM for holding a program code for erase/record commands;   a random access memory (RAM) unit for holding erase/record data;   a central processing unit coupled to the hidden ROM, the RAM unit and the inter-integrated interface circuit, wherein the central processing unit receives the erase/record commands and data passing through the inter-integrated circuit interface circuit and then stores the erase/record data in the RAM unit, while the erase/record commands are decoded by referring to the program code in the hidden ROM after which the decoded commands are re-transmitted; and   an erase/record control register coupled to the central processing unit for receiving the decoded erase/record commands and converting the erase/record commands into the interface control signals or erase/read/write signals, and converting the erase/record data stored in the RAM unit into address and data signals.   
     
     
       21. The system of  claim 19 , wherein the erase/record command decoder is a hardware circuit that separates each erase/record command picked up by the inter-integrated circuit into a plurality of states for ease of decoding and converts the erase/record commands and data into erase/read/write, address and data signals. 
     
     
       22. The system of  claim 16 , wherein the mode return device further includes:
 a mode return control register for receiving the address, data and read/write signals and producing a mode return signal as soon as a reprogramming operation is finished; and   a mode return circuit coupled to the mode return control register and the activation device for sending a stop signal to the activation device after receiving the mode return signal so that the activation device switches connection from the erase/record pathway back to the video pathway.   
     
     
       23. The system of  claim 13 , wherein the ROM unit inside the monitor controller is a flash ROM unit. 
     
     
       24. The system of  claim 13 , wherein the ROM unit comprises an erasable programmable ROM unit. 
     
     
       25. A method for reprogramming the function of a liquid crystal display (LCD) monitor system, comprising the steps of:
 tapping a plurality of signals from a set of video graphic adapter (VGA) signal lines to perform a plurality of consecutive address sequence comparisons with a pre-set address sequence;   triggering a programming mode inside the LCD monitor system when one of the tapped consecutive address sequences matches that of the pre-set address sequence;   reading an erase/record command and deciding what actions to take as soon as the programming mode is activated;   reading in erase/record data and writing the erase/record data into a memory unit when the erase/record command is for a write operation, and then returning to the previous step; and   returning to the very first step when the erase/record command demands a return to a non-programming mode.   
     
     
       26. The method of  claim 25 , wherein reprogramming starts only when the LCD monitor system is not operating in a normal mode. 
     
     
       27. The method of  claim 25 , wherein the LCD monitor system continues to operate in a normal video transmission mode when the tapped consecutive address sequence does not match any pre-set address sequence. 
     
     
       28. A display device for reprogramming the function of a display system, comprising:
 a signal detector for detecting one or more first signals transmitted through one or more video signal lines and determining whether to generate one or more second signals indicative of a switching from a normal mode to a reprogramming mode according to the one or more first signals;   an activation and command decoder device, coupled to the signal detector, and switching from the normal mode to the reprogramming mode in response to the one or more second signals, wherein   in the normal mode, the activation and command decoder device transmits one or more third signals transmitted through the one or more video signal lines to the one or more imaging-processing circuits for receiving image processing, and   in the reprogramming mode, the activation and command decoder device converts one or more fourth signals into one or more fifth signals for modifying a content of a memory within the display system so as to reprogram the function of the display system.   
     
     
       29. The display device of claim 28, wherein in the reprogramming mode, the one or more fourth signals comprise recording commands and recording data, and the one or more fifth signals comprises erase/read/write signals and addresses and data signals such that the content of the memory is modified according to the erase/read/write signals and the addresses and data signals. 
     
     
       30. The display device of claim 28, wherein in the reprogramming mode, the one or more second signals comprise video signals such that the image processing is performed on the video signals. 
     
     
       31. The display device of claim 28, wherein the signal detector determines whether a consecutive address sequence represented by the one or more first signals matches that of a pre-set address sequence and generates the one or more second signals indicative of a switching from the normal mode to the reprogramming mode if it determines that the consecutive address sequence matches that of the pre-set address sequence. 
     
     
       32. The display device of claim 28, wherein the one or more video signal lines are one or more VGA signal lines. 
     
     
       33. The display device of claim 28, wherein the memory is a non-volatile memory. 
     
     
       34. The display device of claim 28, wherein the activation and command decoder device switches from the normal mode to the reprogramming mode by switching from a video path to a recording path. 
     
     
       35. A display system, comprising:
 one or more video signal lines;   a memory for storing data related to the function of the display system;   a display device, coupled to the one or more video signal lines and the memory, for receiving one or more first signals transmitted through the one or more video signal lines and determining whether to switch from a normal mode to a reprogramming mode according to the one or more first signals, wherein   in the normal mode, the display device receives one or more second signals transmitted through the one or more video signal lines and controls the one or more second signals to receive image processing, and   in the reprogramming mode, the display device receives one or more third signals transmitted through the one or more video signal lines and modifies a content of the memory so as to reprogram the function of the display system according to the one or more third signals.   
     
     
       36. The display system of claim 35, wherein in the reprogramming mode, the one or more third signals comprise recording commands and recording data such that the content of the memory is modified according to the recording commands and the recording data. 
     
     
       37. The display system of claim 36, wherein the display device further determines whether to return to the normal mode from the reprogramming mode according to the recording commands. 
     
     
       38. The display system of claim 36, wherein in the reprogramming mode, the display device converts the recording commands into erase/read/write signals and converting the recording data into addresses and data signals so as to modify the content of the memory according to the erase/read/write signals and the addresses and data signals. 
     
     
       39. The display system of claim 35, wherein in the reprogramming mode, the one or more second signals comprise video signals such that the image processing is performed on the video signals. 
     
     
       40. The display system of claim 35, wherein the display device determines whether a consecutive address sequence represented by the one or more first signals matches that of a pre-set address sequence and determines to switch to the reprogramming mode if it determines that the consecutive address sequence matches that of the pre-set address sequence. 
     
     
       41. The display system of claim 35, wherein the one or more video signal lines are one or more VGA signal lines. 
     
     
       42. The display system of claim 35, wherein the memory is a non-volatile memory. 
     
     
       43. The display system of claim 35, wherein the display device switches from the normal mode to the reprogramming mode by switching from a video path arranged for transmitting the one or more second signals to one or more imaging-processing circuits, to a recording path arranged for transmitting the one or more second signals to a decoder coupled to the memory. 
     
     
       44. The display system of claim 35, wherein the display device switches from the normal mode to the reprogramming mode by switching from a video path coupled to one or more imaging-processing circuits for performing the image processing, to a recording path coupled to the memory. 
     
     
       45. A method for reprogramming the function of a display system, comprising:
 receiving one or more first signals transmitted through one or more video signal lines and determining whether to switch from a normal mode to a reprogramming mode according to the one or more first signals;   in the normal mode, receiving one or more second signals transmitted through the one or more video signal lines and performing image processing based on the one or more second signals; and   in the reprogramming mode, receiving one or more third signals transmitted through the one or more video signal lines and modifying a content of a memory within the display system so as to reprogram the function of the display system according to the one or more third signals.   
     
     
       46. The method of claim 45, wherein in the reprogramming mode, the one or more third signals comprise recording commands and recording data such that the content of the memory is modified according to the recording commands and recording data. 
     
     
       47. The method of claim 46, further comprising determining whether to return to the normal mode from the reprogramming mode according to the recording commands. 
     
     
       48. The method of claim 46, wherein in the reprogramming mode, the modifying step of the content of the memory comprises:
 converting the recording commands into erase/read/write signals and converting the recording data into addresses and data signals for modifying the content of the memory.   
     
     
       49. The method of claim 45, wherein in the reprogramming mode, the one or more second signals comprise video signals such that the image processing step is performed on the video signals. 
     
     
       50. The method of claim 45, wherein the determining step comprising:
 determining whether a consecutive address sequence represented by the one or more first signals matches that of a pre-set address sequence; and   switching to the reprogramming mode if the consecutive address sequence is determined to match that of the pre-set address sequence.   
     
     
       51. The method of claim 45, wherein the one or more video signal lines are one or more VGA signal lines. 
     
     
       52. The method of claim 45, wherein the memory is a non-volatile memory. 
     
     
       53. The method of claim 45, wherein the switching step from the normal mode to the reprogramming mode comprises switching from a video path arranged for transmitting the one or more second signals to imaging-processing circuits, to a recording path arranged for transmitting the one or more third signals to a decoder coupled to the memory. 
     
     
       54. The method of claim 45, wherein the switching step from the normal mode to the reprogramming mode comprises switching from a video path coupled to one or more imaging-processing circuits for performing the image processing, to a recording path coupled to the memory.