System for providing access of multiple data buffers to a data retaining and processing device

Abstract

An area efficient system that includes a first circuit to synchronize a clock signal and a data signal and a data retaining and processing device to receive data from said data bus to thereby generate a status signal indicating the receipt of data by said area efficient system; a reference bus address and said data bus. The system also includes a device to compare the reference bus address with the content of memory for generating an address matching signal and a control signal generator to govern the data write signal generation for said shifting means. The system further includes a sequencer to read and write data from/to said data retaining and processing device in a plurality of subcycles for efficiently accessing storage buffers and a direct storage access controlling means for generating interrupt signals and access request signals.

What is claimed is: 
     
       1. An area efficient system for providing serial access of multiple data buffers to a data retaining and processing device, comprising:
 a signal synchronization and detection means operable to synchronize a clock signal and a data signal, said data signal being used with said clock signal for generating status signals on a data bus; 
 a shift register operable to receive and retain data received from said data bus and to generate: 
 aat least one status signal indicating the receipt of data by said area efficient system; and  
 a reference bus address; and 
 said data for enabling direct storage access; 
 a comparator operably coupled to at least three storage areas and configured to compare said reference bus address with the content of at least one of said storage areas to generate an address matching signal; 
 a control signal module connected and operable to govern a data write signal generation for said shift register responsive to said data bus; and  
 a sequencer configured to read data from said data retaining and processing device and writing to write data to said data retaining and processing device in a plurality of sub-cycles responsive to said status signals, data bus, said address matching signal, and said reference bus address;, 
 said sequencer further comprising a direct storage access controller operably coupled to at least three address registers, said address registers connected to communicate with said multiple data buffers, for enabling said direct storage access controller configured to enable data read and write operation operations of said data retaining and processing device, receiving to receive signals from said shift register for enabling speed efficient access of said a data bus to said data retaining and processing device and receiving to receive a control signal from said sequencer for generating interrupt signals and access request signals for said data retaining and processing device; and,  
 said serial access of said multiple data buffers being performed according to the inter-integrated circuit data transfer protocol. 
 
     
     
       2. The system of  claim 1 , wherein said at least one status signals signal further comprise comprises at least one of:
 a data transfer commencement signal; 
 a data transfer completion signal; 
 an acknowledgement signal; 
 a bus error detection signal; and 
 a data sampling signal. 
 
     
     
       3. The system of  claim 1 , wherein said data retaining and processing device is a micro controller microcontroller. 
     
     
       4. The system of  claim 1 , wherein said data retaining and processing device is a microprocessor. 
     
     
       5. The system of  claim 1 , wherein said signal synchronization and detection means comprises:
 a filter connected to receive the clock signal; and 
 a data bus operations detector coupled to said filter and said data bus. 
 
     
     
       6. The system of  claim 1 , wherein said control signal module generates write signals for writes between the shift register and at least one data register. 
     
     
       7. The system of  claim 1 , wherein said sequencer comprises a state machine. 
     
     
       8. The system of  claim 1 , wherein said direct storage access controller comprises:
 a direct memory access controller; and 
 an interrupt signal generation means for generating at least one interrupt signal and at least one access request signal. 
 
     
     
       9. A microcontroller containing a plurality of macrocells, each macrocell comprising:
 a signal synchronization and detection means operable to synchronize a clock signal and a data signal, said data signal being used with said clock signal for generating status signals on a data bus; 
 a shift register operable to receive and retain data received from said data bus and to generate: 
 aat least one status signal indicating the receipt of data by said area efficient system; and  
 a reference bus address; and 
 said data for enabling direct storage access; 
 a comparator operably coupled to at least three storage areas and configured to compare said reference bus address with the content of at least one of said storage areas to generate an address matching signal; 
 a control signal module connected and operable to govern a data write signal generation for said shift register responsive to said data bus; and  
 a sequencer configured to read data from said a data retaining and processing device and writing to write data to said data retaining and processing device in a plurality of sub-cycles responsive to said at least one status signals data bus signal, address matching signal, and said reference bus address;, 
 said sequencer further comprising a direct storage access controller operably coupled to at least three address registers, said address registers connected to communicate with said multiple data buffers, for enabling said direct storage access controller configured to enable data read and write operation operations of said data retaining and processing device, receiving to receive signals from said shift register for enabling speed efficient access of said a data bus to said data retaining and processing device and receiving to receive a control signal from said sequencer for generating interrupt signals and access request signals for said data retaining and processing device; and,  
 said serial access of said multiple data buffers being performed according to the inter-integrated circuit data transfer protocol. 
 
     
     
       10. The microcontroller of  claim 9 , wherein said at least one status signals signal further comprise comprises at least one of:
 a data transfer commencement signal; 
 a data transfer completion signal; 
 an acknowledgement signal; 
 a bus error detection signal; and 
 a data sampling signal. 
 
     
     
       11. The microcontroller of  claim 9 , wherein said data retaining and processing device is a micro controller. 
     
     
       12. The microcontroller of  claim 9 , wherein said data retaining and processing device is a microprocessor. 
     
     
       13. The microcontroller of  claim 9 , wherein said signal synchronization and detection means comprises:
 a filter connected to receive the clock signal; and 
 a data bus operations detector coupled to said filter and said data bus. 
 
     
     
       14. The microcontroller of  claim 9 , wherein said control signal module generates write signals for writes between the shift register and at least one data register. 
     
     
       15. The microcontroller of  claim 9 , wherein said sequencer comprises a state machine. 
     
     
       16. The microcontroller of  claim 9 , wherein said direct storage access controller comprises:
 a direct memory access controller; and 
 an interrupt signal generation means for generating at least one interrupt signal and at least one access request signal. 
 
     
     
       17. A method of providing serial access of multiple data buffers to a data retaining and processing device, the method comprising:
 synchronizing a clock signal and a data signal, said data signal being used with said clock signal for generating at least one status signals on a data bus signal; 
 receiving and retaining data received from said data bus and to generate:; 
 generating a status signal indicating the receipt of said data by said area efficient system;, and a reference bus address; and 
 said data for enabling direct storage access; 
 in at least three storage areas, comparing said reference bus address with the content of said at least one of three storage areas to generate an address matching signal; 
 generating a data write signal for said shift register responsive to said data bus; 
 reading data from said data retaining and processing device and writing data to said data retaining and processing device in a plurality of sub-cycles responsive to said at least one status signals, data bus, signal, said address matching signal, and said reference bus address; and  
 in at least three address registers, said address registers connected to communicate with said multiple data buffers, enabling data read and write operation of said a data retaining and processing device, receiving signals from said shift register for enabling speed efficient access of said data bus to said data retaining and processing device and receiving a control signal from said sequencer for generating at least one of each of an interrupt signals signal and an access request signals signal for said data retaining and processing device; and,  
 said serial access of said multiple data buffers being performed according to the inter-integrated circuit data transfer protocol. 
 
     
     
       18. An area efficient system for providing serial access of multiple data buffers to a data retaining and processing device, the system comprising:
 a signal synchronization and detection subsystem configured to synchronize a clock signal and a data signal upon which a status signal is based; and   a data storage and associated control subsystem configured to receive data, to generate a status signal indicating receipt of said data, a reference bus address, and an address matching signal responsive to comparison of a reference bus address with content of a plurality of storage areas,   said data storage and associated control subsystem configured to read data from said data retaining and processing device and to write data to said data retaining and processing device according to the inter-integrated circuit data transfer protocol in a plurality of sub-cycles responsive to said status signal, said address matching signal, and said reference bus address,   said data storage and associated control subsystem coupled to a plurality of address registers each respectively corresponding to one of said plurality of storage areas, said address registers configured to communicate with said multiple data buffers, and   said data storage and associated control subsystem configured to enable data read and write operations on said data retaining and processing device, to receive signals enabling access by said data retaining and processing device to a data bus, and to receive a control signal for generating an interrupt signal and an access request signal for said data retaining and processing device.   
     
     
       19. The system of claim 18, wherein said data storage and associated control subsystem comprises:
 a shift register configured to receive and retain data and to generate said status signal, said reference bus address, and said data enabling direct storage access.   
     
     
       20. The system of claim 19, wherein said data storage and associated control subsystem comprises:
 a control signal module configured to govern data write signal generation for said shift register.   
     
     
       21. The system of claim 18, wherein said data storage and associated control subsystem comprises:
 a comparator operably coupled to said plurality of storage areas and configured to compare said reference bus address with said content of said storage areas to generate said address matching signal.   
     
     
       22. The system of claim 18, wherein said data storage and associated control subsystem comprises:
 a sequencer configured to read data from said data retaining and processing device and to write data to said data retaining and processing device according to the inter-integrated circuit data transfer.   
     
     
       23. The system of claim 22, wherein said sequencer comprises:
 a direct storage access controller coupled to said plurality of address registers and configured to enable data read and write operations of said data retaining and processing device, to receive a signal from said shift register for enabling speed efficient access of said data bus to said data retaining and processing device, and to receive a control signal from said sequencer for generating the interrupt signal and the access request signal for said data retaining and processing device.   
     
     
       24. A method of providing serial access of multiple data buffers to a data retaining and processing device, the method comprising:
 synchronizing a clock signal and a data signal, said data signal being used with said clock signal for generating a status signal;   receiving and retaining data;   generating said status signal indicating receipt of said data and a reference bus address;   comparing said reference bus address with content of a plurality of storage areas to generate an address matching signal;   reading data from said data retaining and processing device and writing data to said data retaining and processing device according to the inter-integrated circuit data transfer protocol in a plurality of sub-cycles responsive to said status signal, said address matching signal, and said reference bus address;   in a plurality of address registers each respectively corresponding to one of said plurality of storage areas, said address registers configured to communicate with said multiple data buffers, enabling data read and write operations of said data retaining and processing device, receiving a signal from said shift register for enabling access by said data retaining and processing device to a data bus, and receiving a control signal for generating an interrupt signal and an access request signal for said data retaining and processing device.   
     
     
       25. The method of claim 24, further comprising:
 shifting said data received into a shift register.   
     
     
       26. The method of claim 25, further comprising:
 governing data write signal generation for said shift register.   
     
     
       27. The method of claim 24, further comprising:
 employing a plurality of comparators each coupled respectively to one of said plurality of storage areas to compare said reference bus address with said content of said storage areas to generate said address matching signal.   
     
     
       28. The method of claim 24, further comprising:
 employing a sequencer to read data from said data retaining and processing device and to write data to said data retaining and processing device according to the inter-integrated circuit data transfer.   
     
     
       29. The method of claim 28, further comprising:
 employing a direct storage access controller within said sequencer and coupled to said plurality of address registers to enable data read and write operations of said data retaining and processing device, receiving the signal from said shift register for enabling access by said data retaining and processing device to said data bus, and receiving the control signal for generating the interrupt signal and the access request signal for said data retaining and processing device.