Bipolar method and structure having improved BVCEO/RCS trade-off made with depletable collector columns

Abstract

In accordance with the invention, there are various methods of making an integrated circuit comprising a bipolar transistor. According to an embodiment of the invention, the bipolar transistor can comprise a substrate, a collector comprising a plurality of alternating doped regions, wherein the plurality of alternating doped regions alternate in a lateral direction from a net first conductivity to a net second conductivity, and a collector contact in electrical contact with the collector. The bipolar transistor can also comprise a heavily doped buried layer below the collector, a base in electrical contact with a base contact, wherein the base is doped to a net second conductivity type and wherein the base spans a portion of the plurality of alternating doped regions, and an emitter disposed within the base, the emitter doped to a net first conductivity, wherein a portion of the alternating doped region under the emitter is doped to a concentration of less than about 3×10 12 cm −2 .

The invention claimed is: 
     
       1. An integrated circuit comprising a bipolar transistor comprising:
 a substrate;   a collector comprising a plurality of alternating doped regions, wherein the plurality of alternating doped regions alternate in a lateral direction from a net first conductivity to a net second conductivity;   a collector contact in electrical contact with the collector;   a heavily doped buried layer below the collector;   a base in electrical contact with a base contact, wherein the base is doped to the net second conductivity type and wherein-the base spans a portion of the plurality of alternating doped regions; and   an emitter disposed totally within the base, the emitter doped to the net first conductivity, wherein a portion of the alternating doped region under the emitter is doped to a concentration of less than about 3×10 12  cm −2  in the lateral direction.   
     
     
       2. The integrated circuit comprising a bipolar transistor according to  claim 1 , wherein the portion of the alternating doped region under the emitter is doped to a concentration of less than about 2×10 12  cm −2  in a lateral direction. 
     
     
       3. The integrated circuit comprising a bipolar transistor according to  claim 1 , wherein a portion of the alternating doped regions disposed beneath the emitter is doped to a net first conductivity type. 
     
     
       4. The integrated circuit comprising a bipolar transistor according to  claim 3 , wherein a width of the doped region disposed beneath the emitter is substantially the same as a width of the emitter. 
     
     
       5. The integrated circuit comprising a bipolar transistor according to  claim 3 , wherein the doped region disposed beneath the emitter extends from the base to the more heavily doped buried layer. 
     
     
       6. The integrated circuit comprising a bipolar transistor according to  claim 5 , wherein the length, as defined from the base to the buried layer, of the alternating doped region under the emitter is defined by BV CEO /E crit . 
     
     
       7. The integrated circuit comprising a bipolar transistor according to  claim 1  further comprising:
 an electrical sinker in electrical contact with the collector contact and in electrical contact with the more heavily doped buried layer. 
 
     
     
       8. The integrated circuit comprising a bipolar transistor according to  claim 3  farther comprising:
 at least one doped second region disposed adjacent to the doped region disposed under the emitter, wherein the at least one doped second region is doped to a net second conductivity type. 
 
     
     
       9. The integrated circuit comprising a bipolar transistor according to  claim 8 , wherein the doped region disposed beneath the emitter depletes at a reverse bias collector base voltage of magnitude less than an absolute value of BV CEO . 
     
     
       10. The integrated circuit comprising a bipolar transistor according to  claim 8 , wherein the doped second regions disposed adjacent to the doped region disposed beneath the emitter depletes under a reverse bias collector voltage less than BV CEO . 
     
     
       11. The integrated circuit comprising a bipolar transistor according to  claim 1 , further comprising a second bipolar transistor, wherein the bipolar transistor has a breakdown voltage greater than the second bipolar transistor. 
     
     
       12. The integrated circuit comprising a bipolar transistor according to  claim 8 , wherein the doped second regions disposed adjacent to the doped region disposed beneath the emitter do not totally deplete at a magnitude of collector base voltage less than the magnitude of the BVCEO breakdown voltage. 
     
     
       13. The integrated circuit comprising a bipolar transistor according to  claim 1 , wherein an integral across the width of the doped region under the emitter has a value of less than about 3E12 ions/cm 2 . 
     
     
       14. The integrated circuit comprising a bipolar transistor according to  claim 1 , wherein the portion of doped region under the emitter is self aligned to the emitter. 
     
     
       15. An integrated circuit comprising a bipolar transistor comprising:
 a substrate;   a base formed in the substrate;   a collector comprising a doped first region doped to a net first conductivity disposed under the base, to cover the base and doped second regions doped to a net second conductivity disposed on opposite sides of the doped first region; wherein the base is doped to the net second conductivity type;   a collector contact in electrical contact with the collector;   a more heavily doped layer buried below the doped first region and the doped second regions; and   an emitter doped to the net first conductivity disposed within the base, wherein the doped region disposed beneath the emitter depletes at a reverse bias collector base voltage of magnitude less than an absolute value of BV CEO .   
     
     
       16. The integrated circuit comprising a bipolar transistor according to  claim 15 , wherein the doped second regions disposed adjacent to the doped first region do not totally deplete under reverse bias of the collector to base junction. 
     
     
       17. The integrated circuit comprising a bipolar transistor according to  claim 15 , wherein the bipolar transistor is an NPN bipolar transistor comprising a BV CEO  of at least 69 Volts. 
     
     
       18. The integrated circuit comprising a bipolar transistor according to  claim 15 , wherein the bipolar transistor is a PNP bipolar transistor comprising a BV CEO  of at least 82 Volts. 
     
     
       19. The integrated circuit comprising a bipolar transistor according to  claim 15 , wherein the bipolar transistor is an NPN bipolar transistor, and wherein the collector is doped with at least about 2×10 15  atoms/cm 3 . 
     
     
       20. The integrated circuit comprising a bipolar transistor according to  claim 15 , wherein the bipolar transistor is an NPN bipolar transistor, and wherein first doped region has a length of about 4 μm to about 6 μm, and further wherein the first doped region has a width of about 7 μm to about 9 μm. 
     
     
       21. The integrated circuit comprising a bipolar transistor according to  claim 15 , wherein the bipolar transistor is a PNP bipolar transistor, and wherein the collector is doped with at least about 4×10 15  atoms/cm 3 . 
     
     
       22. The integrated circuit comprising a bipolar transistor according to  claim 15 , wherein the bipolar transistor is a PNP bipolar transistor, and wherein first doped region has a length of about 3 μm to about 5 μm, and further wherein the first doped region has a width of about 3 μm to about 5 μm. 
     
     
       23. The integrated circuit comprising a bipolar transistor according to  claim 18 , further comprising:
 a PNP bipolar transistor comprising a BV CEO  of at least 82 Volts.   
     
     
       24. The integrated circuit comprising a bipolar transistor according to  claim 15 , wherein the doped region disposed beneath the emitter is self aligned to the emitter. 
     
     
       25. A method of making a bipolar transistor, the method comprising:
 forming a device layer of a first type conductivity over a substrate;   forming a patterned layer over the device layer, wherein the patterned layer comprises an opening that exposes a portion of the device layer;   providing dopants of a second conductivity type to the exposed portion of the device layer to form a column of second conductivity type dopants in the device layer;   providing dopants of the first conductivity type to the exposed portion of the device layer to form an intrinsic base in the device layer;   forming an emitter that contacts a portion of the exposed device layer; and   forming an emitter contact over the emitter.   
     
     
       26. The method of claim 25, wherein forming the device layer of the first type conductivity over the substrate comprises forming the device layer of a first type conductivity over a heavily doped substrate. 
     
     
       27. A method of making a bipolar transistor, the method comprising:
 forming a device layer over a substrate;   forming a patterned insulator over the device layer, wherein the patterned insulator comprises a first opening that exposes a first portion of the device layer;   providing dopants of a conductivity type to the exposed first portion of the device layer to form a base in the device layer;   forming a patterned base insulator over the exposed first portion of the device layer, wherein the patterned base insulator comprises a second opening that exposes an area of the first portion of the device layer;   providing dopants of a second conductivity type to the exposed area of the first portion of the device layer to form a column of second conductivity type dopants in the device layer; and   forming an emitter that contacts a portion of the exposed area of the first portion of the device layer.   
     
     
       28. The method of claim 27, wherein the conductivity type is a first conductivity type wherein forming the device layer over the substrate comprises forming the device layer having a second conductivity type. 
     
     
       29. The method of claim 27, wherein forming the device layer over the substrate comprises forming the device layer over a heavily doped substrate. 
     
     
       30. A method of making a bipolar transistor, the method comprising:
 forming a device layer having a first conductivity type over a substrate;   forming first heavily doped buried regions of the first conductivity type in first portions of the device layer;   forming second heavily doped buried regions of a second conductivity type in second portions of the device layer;   forming an epitaxial layer having the first conductivity type over the device layer;   forming two regions of the second conductivity type over at least one of the first heavily doped buried regions of the first conductivity type; and   forming one region of the second conductivity type over at least one of the second heavily doped buried regions of the second conductivity type.   
     
     
       31. The method of claim 30, wherein forming the epitaxial layer having the first conductivity type over the device layer comprises forming a first epitaxial layer having the first conductivity type over the device layer, the method further comprising:
 forming a second epitaxial layer having the first conductivity type over the first epitaxial layer.   
     
     
       32. The method of claim 30, further comprising:
 masking the epitaxial layer with a mask layer to provide openings to allow ions of the second conductivity type to be implanted in the epitaxial layer.   
     
     
       33. The method of claim 30, further comprising:
 heating the formed layers to diffuse and form columns of the second conductivity type in the epitaxial layer.   
     
     
       34. The method of claim 33, wherein the first conductivity type is N-type and the second conductivity type is P-type, wherein heating the formed layers comprises:
 diffusing and forming at least one P-type column in an NPN collector over at last one of the first heavily doped buried regions of the first conductivity type in the first portions of the device layer; and   diffusing and forming at least one P-type column in a PNP collector over at last one of the second heavily doped buried regions of a second conductivity type in second portions of the device layer.   
     
     
       35. The method of claim 33, wherein the first conductivity type is P-type and the second conductivity type is N-type, wherein heating the formed layers comprises:
 diffusing and forming at least one N-type column in a PNP collector over at last one of the first heavily doped buried regions of the first conductivity type in the first portions of the device layer; and   diffusing and forming at least one N-type column in an NPN collector over at last one of the second heavily doped buried regions of the second conductivity type in second portions of the device layer.   
     
     
       36. A method of making a bipolar transistor with a base, an emitter, and a collector, which are self aligned to each other, the method comprising:
 forming a device layer having a first conductivity type on a buried layer doped with a second conductivity type;   forming an oxide layer over a base contact layer overlaying the device layer so as to expose a portion of the device layer that will form a device region;   patterning a base contact in the device region;   exposing the device layer through a hole in the base contact;   implanting and diffusing ions having the second conductivity type so as to form a column in a first region of the device layer;   forming a base by implanting ions having the first conductivity type using the base contact as a mask; and   annealing the base implant so that the base is contacted by the base contact.   
     
     
       37. The method of claim 36, wherein forming a device layer having the first conductivity type comprises forming an epitaxial layer having the first conductivity type. 
     
     
       38. The method of claim 37, wherein diffusing the ions having the second conductivity type so as to form the column in the epitaxial layer comprises forming the column to span a thickness of the epitaxial layer so as to contact the buried layer. 
     
     
       39. The method of claim 36, further comprising:
 implanting ions having the second conductivity type into a second region of the device layer having the first conductivity type.   
     
     
       40. The method of claim 39, further comprising:
 patterning a collector contact over the ions having the second conductivity type in the second region of the device layer while patterning the layer of conducting material to form the emitter contact.   
     
     
       41. The method of claim 36, further comprising:
 forming spacers on sidewalls of the hole in the base contact;   depositing a layer of conducting material over the device region; and   patterning the layer of conducting material to form an emitter contact disposed between the sidewall spacers, wherein the self-aligned emitter contacts the device layer.   
     
     
       42. The method of claim 36, wherein forming the device layer having the first conductivity type on the buried layer having the doped second conductivity type comprises
 forming the device layer having the first conductivity type on the buried layer heavily doped in the second conductivity type.   
     
     
       43. A method of making a bipolar transistor comprising:
 forming an epitaxial layer having a first conductivity type on a buried layer having a doped second conductivity type;   growing an insulator over the epitaxial layer and implanted ions;   diffusing the implanted ions into the epitaxial layer to form a sinker that contacts the buried layer;   patterning the insulator layer to expose a portion of the epitaxial layer that will form a device region;   forming a base of the first conductivity type in the exposed portion;   growing a base oxide over the base of the first conductivity type;   forming an opening through the base oxide using a patterned photoresist so as to expose an area of a device layer;   forming a collector column of the second conductivity type using the patterned photoresist;   diffusing and activating the collector column;   forming an emitter heavily doped with the second conductivity type in the base wherein an emitter area is defined in the opening; and   forming an emitter positioned above the collector column in a surface of the base.   
     
     
       44. The method of claim 43, further comprising
 implanting ions having the second conductivity type into a first region of the epitaxial layer having the first conductivity type;   growing an insulator over the device layer and the implanted ions; and   diffusing the implanted ions into the device layer to form a sinker that contacts the buried layer.   
     
     
       45. The method of claim 43, further comprising forming emitter poly heavily doped with the second conductivity type over the opening wherein the emitter area is defined in the opening where the emitter poly contacts the base. 
     
     
       46. The method of claim 43, wherein forming an emitter positioned above the collector column comprises forming the emitter self-aligned above the collector column. 
     
     
       47. The method of claim 43, further comprising
 exposing a base contact region; and   depositing a metal layer to form base contact metal, emitter contact metal, and collector contact metal through patterned trenches, wherein the base, the emitter, and the collector column are self aligned.   
     
     
       48. The method of claim 43, wherein the collector column spans the thickness of the epitaxial layer so as to contact the buried layer.