Semiconductor memory device and module for high frequency operation

Abstract

The present invention relates to a synchronous semiconductor memory device with double data rate, and more particularly, to a synchronous semiconductor memory device for inputting and outputting data using a free-running clock and inserting a preamble indicative of start of data into the outputted data. A semiconductor memory device of the present invention receives a data read command from the exterior of the memory device in response to a predetermined clock signal inputted from the exterior, and outputting data including a preamble in response to the clock signal.

What is claimed is: 
     
       1. A semiconductor memory device comprising:
 a memory cell for storing data; 
 an internal clock generator for generating a first internal clock signal, a second internal clock signal or a third internal clock signal in response to a mode control signal; 
 a command/address input unit for transferring an externally input command/address signal to inside of the semiconductor memory device in synchronization with the first internal clock signal; 
 a controller for outputting a plurality of control signals and an address signal in response to the command/address signal so as to control operation of the semiconductor memory device, the controller having a mode register for generating the mode control signal; 
 a control circuit for selecting between a first mode and a second mode in response to the mode control signal, wherein in the first mode the control circuit selects both of an externally input first clock signal and an externally input second clock signal and in the second mode the control circuit selects only one of the externally input first clock signal and the externally input second clock signal; 
 a data input unit for receiving data in synchronization with the second internal clock signal; 
 a data output unit for outputting data including a preamble in synchronization with the third internal clock signal; and 
 a data processing unit for storing data inputted through the data input unit in the memory cell according to the control signals of the control unit, or transferring the data from the memory cell to the data output unit, wherein the preamble is added to a header of the outputted data and is indicative of start of the data; 
 wherein:
 in the first mode the internal clock generator generates the first internal clock signal in response to the externally input first clock signal, and generates the second internal clock signal or the third internal clock signal in response to a predetermined control signal and the externally input second clock signal, and 
 in the second mode the internal clock generator generates the first internal clock signal in response to the one of the externally input first clock signal and the externally input second clock signal, and generates the second internal clock signal or the third internal clock signal in response to a predetermined control signal and the one of the externally input first clock signal and the externally input second clock signal. 
 
 
     
     
       2. The semiconductor memory device of  claim 1 , wherein the preamble added to each data outputted through the data lines has the same level. 
     
     
       3. The semiconductor memory device of  claim 1 , wherein the level of the preamble is a high level. 
     
     
       4. The semiconductor memory device of  claim 1 , wherein the level of the preamble is a low level. 
     
     
       5. The semiconductor memory device of  claim 1 , wherein the preamble added to data outputted through neighboring data lines among the plurality of data lines has different level. 
     
     
       6. The semiconductor memory device of  claim 1 , wherein, in the second mode, the semiconductor memory device generates the first to third internal clock signals using the externally input first clock signal. 
     
     
       7. The semiconductor memory device of  claim 1 , wherein, in the second mode, the semiconductor memory device generates the first to third internal clock signals using the externally input second clock signal. 
     
     
       8. The semiconductor memory device of  claim 1 , wherein if data including the preamble from the outside, the semiconductor memory device detects the preamble included in the input data unit to latch an input data. 
     
     
       9. The semiconductor memory device of  claim 8 , wherein the data input unit further comprises:
 a preamble detecting circuit for latching inputted data including the preamble; and 
 a data input buffer for inputting an input data in synchronization with the second internal clock signal to the data input unit according to a preamble detection signal from the preamble detection circuit. 
 
     
     
       10. A semiconductor memory device inputting and outputting data including a preamble, the semiconductor memory device comprising:
 a memory cell for storing data through a plurality of data lines; 
 an internal clock generator for generating a first internal clock signal, a second internal clock signal or a third internal clock signal in response to a mode control signal; 
 a command/address input unit for transferring an externally input command/address signal to inside of the semiconductor memory device in synchronization with the internal command/address clock signal; 
 a controller for outputting a plurality of control signals and an address signal in response to the command/address signal so as to control operation of the semiconductor memory device, the controller having a mode register for generating the mode control signal; 
 a control circuit for selecting between a first mode and a second mode in response to the mode control signal, wherein in the first mode the control circuit selects both of an externally input first clock signal and an externally input second clock signal and in the second mode the control circuit selects only one of the externally input first clock signal and the externally input second clock signal; 
 a data input unit for receiving data including a preamble in synchronization with any one of the plurality of internal clock signals; 
 a data output unit for outputting data including a preamble in synchronization with any one of the plurality of internal clock signals; and 
 a data processing unit for storing data inputted through the data input unit in the memory cell according to a control signal of the control unit, or transferring the data from the memory cell to the data output unit, 
 wherein the data output unit comprises a preamble generator for generating the preamble and adding the preamble to the output data, and 
 wherein:
 in the first mode the internal clock generator generates the first internal clock signal in response to the externally input first clock signal, and generates the second internal clock signal or the third internal clock signal in response to a predetermined control signal and the externally input second clock signal, and 
 in the second mode the internal clock generator generates the first internal clock signal in response to the one of the externally input first clock signal and the externally input second clock signal, and generates the second internal clock signal or the third internal clock signal in response to a predetermined control signal and the one of the externally input first clock signal and the externally input second clock signal. 
 
 
     
     
       11. The semiconductor memory device of  claim 10 , wherein the data input unit comprises:
 a preamble detector for detecting a preamble of inputted data and generating a preamble detecting signal; 
 a clock selector for receiving the plurality of internal clock signals and selecting and outputting one of the plurality of internal clock signals in response to the preamble detecting signal; and 
 a data input buffer for receiving inputted data in synchronization with the internal clock signal selected by the clock selector. 
 
     
     
       12. The semiconductor memory device of  claim 11 , wherein the plurality of internal clock signals have different phases from each other. 
     
     
       13. The semiconductor memory device of  claim 12 , wherein the plurality of internal clock signals have phase difference of 45°. 
     
     
       14. A semiconductor memory device comprising:
 a memory portion;   a data terminal;   a data input buffer connected to receive data to be stored in the memory from the data terminal;   a clock selection circuit having an output on which a selected clock is provided, the selected clock corresponding to one of a plurality of internal clock signals and being selected in response to a timing of a preamble signal provided to the semiconductor memory device on the data terminal during a write operation; and   an internal clock generator having a plurality of internal clock outputs on which respective ones of the plurality of internal clock signals are provided,   wherein the clock selection circuit includes a plurality of inputs connected to receive respective ones of the plurality of internal clock signals.   
     
     
       15. The semiconductor memory device of claim 14, further comprising:
 a control circuit having an output provided to the clock selection circuit to control the selection of the clock selection circuit in response to the preamble signal provided on the data terminal.   
     
     
       16. The semiconductor memory device of claim 15, wherein the output of the control circuit is responsive to the preamble signal provided on the data input terminal immediately prior to receipt of data. 
     
     
       17. The semiconductor memory device of claim 15, further comprising:
 a plurality of data terminals,   wherein the data terminal is one of the plurality of data terminals, and   wherein the preamble signal is composed of multiple signals provided on the plurality of data terminals.   
     
     
       18. The semiconductor memory device of claim 17, wherein the semiconductor memory device further comprises a data processing unit configured to store data appended to the preamble received by the data terminals. 
     
     
       19. The semiconductor memory device of claim 18, wherein the control circuit is logically connected to receive signals from all of the data terminals. 
     
     
       20. The semiconductor memory device of claim 17, wherein the data buffer comprises a plurality of latches and the selected clock is provided to the plurality of latches to latch data provided to the data terminals. 
     
     
       21. The semiconductor memory device of claim 20, further comprising an address terminal separate from the data terminals so that address and data are provided on separate terminals to the semiconductor memory device. 
     
     
       22. The semiconductor memory device of claim 17, further comprising an address terminal separate from the data terminal so that address and data are provided on separate terminals to the semiconductor memory device. 
     
     
       23. The semiconductor memory device of claim 17, wherein the data input buffer comprises a plurality of latches and the selected clock is provided to the plurality of latches to latch data provided to the data terminals. 
     
     
       24. The semiconductor memory device of claim 23, further comprising an address terminal separate from the data terminal so that address and data are provided on separate terminals to the semiconductor memory device. 
     
     
       25. The semiconductor memory device of claim 23, wherein the
 plurality of internal clock signals have the same frequency and are out of phase with each other.   
     
     
       26. The semiconductor memory device of claim 25, wherein the plurality of internal clock signals comprise 1 through n internal clock signals having a phase of 1×m through n×m degrees, respectively, where n and m are integers. 
     
     
       27. The semiconductor memory device of claim 25, wherein the plurality of latches are responsive to a latching portion of the selected clock to latch data on corresponding data terminals, and wherein the clock selection circuit is configured to provide the selected clock as the internal clock signal having latching portion near in time to the middle of a data bit receiving period. 
     
     
       28. The semiconductor memory device of claim 27, wherein the latching portion of the selected clock is an edge of the selected clock. 
     
     
       29. A semiconductor memory device comprising:
 data terminals;   a memory;   a data buffer comprising latches to latch in data received on the data terminals to be stored in the memory; and   means for providing an internal clock in response to at least one preamble received on at least one of the data terminals to which at least a portion of the data is appended,   wherein the latches of the data buffer are responsive to the internal clock provided by the means for providing.   
     
     
       30. The semiconductor memory device of claim 29, wherein the means for providing the internal clock provides the internal clock to have a phase responsive to the at least one preamble. 
     
     
       31. The semiconductor memory device of claim 30, further comprising a clock generation circuit to provide a plurality of clocks which are out of phase with each other, and wherein the means for providing an internal clock selects the internal clock from one of the plurality of clocks provided by the clock generation circuit. 
     
     
       32. The semiconductor memory device of claim 29, further comprising a data processing unit having an input to receive the data from the data buffer and an output to store the data in the memory. 
     
     
       33. The semiconductor memory device of claim 29, further comprising an address terminal so that address and data are provided on separate terminals to the semiconductor memory device. 
     
     
       34. A semiconductor memory device comprising:
 data terminals;   a data input buffer connected to receive data from the data terminals;   a memory configured to receive and store the data from the data input buffer; and   a clock selection circuit having an output on which a selected clock is provided, the selected clock corresponding to one of a plurality of internal clock signals and being selected in response to a preamble received by the data input buffer preceding the data on the data terminals and which consists of logic low signals provided on multiple ones of the data terminals,   wherein the preamble to which the clock selection circuit is responsive consists of logic low signals provided on multiple ones of the data terminals during a time period equal to n data input time periods, wherein n is an integer greater or equal to 1.   
     
     
       35. A semiconductor memory device, comprising:
 data terminals;   a data input buffer connected to receive data at each of multiple data input periods from the data terminals;   a memory configured to receive and store the data from the data input buffer; and   a detection circuit to detect a preamble received by the data input buffer preceding the data on the data terminals and which consists of logic low signals provided on multiple ones of the data terminals for a time period no less than multiple data input periods.   
     
     
       36. The semiconductor memory device of claim 35, wherein the preamble to which the clock selection circuit is responsive consists of logic low signals provided on multiple ones of the data terminals during a time period equal to n data input time periods, wherein n is an integer greater or equal to 1. 
     
     
       37. A semiconductor memory device, comprising:
 data terminals including first and second terminals;   a data input buffer connected to receive data from the data terminals;   a memory configured to receive and store the data from the data input buffer; and   a detection circuit to detect a preamble received by the data input buffer preceding the data on the data terminals and which comprises a parallel preamble signal comprising a first logic level on the first terminal and a second logic level, different from the first logic level on the second terminal.   
     
     
       38. The semiconductor memory device of claim 37, wherein the data terminals comprise even terminals and odd terminals, the first terminal is an odd terminal, the second terminal is an even terminal, and the preamble to which the clock selection circuit is responsive is a parallel preamble signal comprising the first logic level on the odd terminals and the second logic level on the even terminals. 
     
     
       39. The semiconductor device of claim 38, wherein the preamble to which the clock selection circuit is responsive is a parallel preamble signal comprising the first logic level on the odd terminals and the second logic level on the even terminals during a time period equal to n data input time periods, wherein n is an integer greater or equal to 2. 
     
     
       40. The semiconductor memory device of claim 37, wherein the preamble to which the clock selection circuit is responsive is a parallel signal preamble comprising the first logic level on the first terminal and the second logic level on the second terminal at a first time period and the second logic level on the first terminal and the first logic level on the second terminal at a second time period immediately following the first time period. 
     
     
       41. The semiconductor memory device of claim 37, wherein the data terminals comprise even terminals and odd terminals, the first terminal is an odd terminal, the second terminal is an even terminal, and the preamble to which the clock selection circuit is responsive is a parallel signal preamble comprising the first logic level on the odd terminals and the second logic level on the even terminals at a first time period and the second logic level on the odd terminals and the first logic level on the even terminals at a second time period immediately following the first time period. 
     
     
       42. The semiconductor memory device of claim 37, wherein the data terminals comprise first, second, third and fourth terminals, and the preamble to which the clock selection circuit is responsive is a parallel signal preamble comprising, during a first time period, the first logic level on the first and fourth terminals and the second logic level on the second and third terminals, and during a second time period immediately following the first time period, the first logic level on the first and third terminals and the second logic level on the second and fourth terminals. 
     
     
       43. The semiconductor device of claim 42, wherein the first, second, third and fourth terminals are nth, nth+1, nth+2 and nth+3 data terminals, respectively.