Wiring layout of semiconductor device and design method of the same

Abstract

A semiconductor device is the semiconductor device which includes more than one field effect transistor having a gate electrode to which an electrical interconnect wire is connected and a gate insulation film with a thickness of 6.0 nm or less and which comprises a first transistor group made up of a plurality of field effect transistors that are the same in thickness of gate insulation film, a second transistor group made up of a plurality of field effect transistors that are the same in thickness of gate insulation film with the thickness of gate insulation film being less than the thickness of the gate insulation film of the first transistor group, and a semiconductor substrate on which the first and second transistor groups are mounted together in a mixed manner, wherein an antenna ratio which is a ratio of the area of a wire to the gate area of a gate electrode is such that the maximum value of the second transistor group is greater than the maximum value of the first transistor group.

1. A semiconductor device including a field effect transistor transistors having a gate electrode with a wire connected thereto and a gate insulation film with a thickness less than or equal to 6.0 nm, said device comprising:
 a first transistor group made up of a plurality of said field effect transistors being the same in thickness of said gate insulation film; 
 a second transistor group made up of a plurality of said field effect transistors being the same in thickness of said gate insulation film, wherein the thickness of said gate insulation film is less than the thickness of said gate insulation film of said first transistor group; and 
 a semiconductor substrate with the first and second transistor groups being mounted thereon in a mixed manner, 
 wherein an antenna ratio which is a ratio of an area of said wire to a gate area of said gate electrode is such that a maximal value of said second transistor group is made larger than a maximal value of said first transistor group. 
 
     
     
       2. The semiconductor device according to  claim 1 , wherein said antenna ratio is such that the maximal value of said second transistor group is made larger by at least one order of magnitude than the maximal value of said first transistor group. 
     
     
       3. The semiconductor device according to  claim 1 , wherein said wire is a multilayered wire, and that the area of said wire is a total area equivalent to a sum of areas of respective layers of said multilayered wire. 
     
     
       4. The semiconductor device according to  claim 3 , wherein said gate electrode and said semiconductor substrate are conducted by the n-th layer (n is an integer more than or equal to 2) of said multilayered wire, and wherein
 at a stage of formation of said multilayered wire up to its (n-1)th layer, the area of said wire is a total area equivalent to a sum of areas of portions of respective layers up to said (n−1)th layer of said multilayered wire, which portions are conducted to said gate electrode. 
 
     
     
       5. The semiconductor device according to  claim 3 , wherein the area of said wire is a total area equivalent to a sum of areas of exposed portions of respective layers of said multilayered wire in a state that the portions are conducted to said gate electrode in a fabrication process of said semiconductor device. 
     
     
       6. The semiconductor device according to  claim 3 , wherein each layer of said multilayered wire is connected by a plug, and
 the area of said wire includes an area of said plug. 
 
     
     
       7. The semiconductor device according to  claim 1 , wherein the area of said wire is a total area equivalent to a sum of areas of both side surfaces and an upper surface of said wire. 
     
     
       8. The semiconductor device according to  claim 1 , wherein the area of said wire is an area of an upper surface of said wire. 
     
     
       9. The semiconductor device according to  claim 8 , wherein the area of said wire is the area of said upper surface×2. 
     
     
       10. The semiconductor device according to  claim 1 , wherein an interlayer dielectric film formed above said wire includes a low dielectric constant film. 
     
     
       11. The semiconductor device according to  claim 1 , wherein a functional block comprised of said first transistor group is different in function from a functional block made up of said second transistor group. 
     
     
       12. The semiconductor device according to  claim 11 , wherein said gate insulation films of said first and second transistor groups include a silicon oxide film together,
 said functional block comprised of said first transistor group is at least one of a memory, an I/O circuit, a power supply circuit, an analog filter circuit and a direct current operating circuit, and 
 said functional block made up of said second transistor group is a logic circuit. 
 
     
     
       13. The semiconductor device according to  claim 12 , wherein said memory includes a NAND type EEPROM. 
     
     
       14. The semiconductor device according to  claim 11 , wherein said gate insulation film of said first transistor group includes a high dielectric film,
 said gate insulation film of said second transistor group includes a silicon oxide film, 
 said functional block comprised of said first transistor group is a logic circuit, and 
 said functional block comprised of said second transistor group is at least one of a memory, an I/O circuit, a power supply circuit, an analog filter circuit and a direct current operating circuit. 
 
     
     
       15. A design method of the semiconductor device as recited in  claim 1 , said method comprising:
 displaying said first and second transistor groups on a screen; and 
 automatically wiring on said screen while letting said wire of said first transistor group be such that a first antenna ratio is an allowable value and while letting said wire of said second transistor group be such that a second antenna ratio greater than said first antenna ratio is an allowable value. 
 
     
     
       16. A semiconductor device having gate insulator films less than 6 nm, comprising:
 a first circuit having first transistors with first wirings respectively connected to first gates of said first transistors; and   a second circuit having second transistors with second wirings respectively connected to second gates of said second transistors; and   said first circuit having a first antenna ratio different than a second antenna ratio of said second circuit,   wherein a thickness of a gate insulator film in said second transistors is thinner than a thickness of a gate insulator film in said first transistors,   wherein said first and second antenna ratios are such that the maximal value of said second antenna ratio of said second circuit is more than three times larger than the maximal value of said first antenna ratio of said first circuit.   
     
     
       17. The semiconductor device according to claim 16, comprising:
 said second transistors having a gate insulator film; and   said first transistors having a high-dielectric constant gate insulator film.   
     
     
       18. The semiconductor device according to claim 17, wherein said high-dielectric constant gate insulator film comprises one of hafnium oxide, hafnium silicate, zirconium oxide and zirconium silicate. 
     
     
       19. The semiconductor device according to claim 16, wherein:
 a thickness of a gate insulator film in said first transistors is more than twice as thick as a thickness of a gate insulator film in said second transistors.   
     
     
       20. The semiconductor device according to claim 16, wherein:
 a thickness of said gate insulator film in said first transistors is about 5 nm, and   a thickness of said gate insulator film in said second transistors is about 2.5 nm.   
     
     
       21. The semiconductor device according to claim 16, comprising:
 the maximal value of said second antenna ratio being more than six times greater than the maximal value of said first antenna ratio.   
     
     
       22. The semiconductor device according to claim 21, comprising:
 said first transistors having a gate insulator film thickness more than twice as thick as a gate insulator film thickness in said second transistors.   
     
     
       23. The semiconductor device according to claim 16, comprising:
 an interlayer dielectric film having a low dielectric constant material on at least one of said first transistors and said second transistors.   
     
     
       24. The semiconductor device according to claim 23, wherein said low dielectric constant material comprises one of SiOC, SiOCH, SiOCN, SiO2, SiN and an aromatic series-based organic film. 
     
     
       25. The semiconductor device according to claim 16, comprising:
 said first wirings having a maximum allowable length shorter than a maximum allowable length of said second wirings.   
     
     
       26. The semiconductor device according to claim 16, wherein said first and second antenna ratios uses a sum of areas of exposed wires in a state that said exposed wires are conducted with a gate electrode in one of said first and second transistors during a manufacturing process of said device that generates charged particles. 
     
     
       27. The semiconductor device according to claim 26, comprising:
 determining said antenna ratio using a sum of top and side areas of said exposed wires.   
     
     
       28. The semiconductor device according to claim 26, comprising:
 determining said antenna ratio using a sum of top areas of said exposed wires.   
     
     
       29. The semiconductor device according to claim 26, wherein said sum of areas of exposed wires is defined as (wire width+2*1.3r)*total wire length, wherein said r is a thickness of a dielectric film deposited on said exposed wires. 
     
     
       30. The semiconductor device according to claim 29, wherein said exposed wires are formed by damascene. 
     
     
       31. The semiconductor device according to claim 16, wherein said first circuit is different in function from said second circuit. 
     
     
       32. The semiconductor device according to claim 16, wherein said first circuit is at least one of a memory, an I/O circuit, a power supply circuit, an analog filter circuit, and a direct current operating circuit, and said second circuit is a logic circuit. 
     
     
       33. The semiconductor device according to claim 16, wherein the maximal value of said second antenna ratio is made larger by at least one order of magnitude than the maximal value of said first antenna ratio. 
     
     
       34. The semiconductor device according to claim 33, comprising:
 said second transistors having a gate insulator film; and   said first transistors having a high-dielectric constant gate insulator film.   
     
     
       35. The semiconductor device according to claim 34, wherein said high-dielectric constant gate insulator film comprises one of hafnium oxide, hafnium silicate, zirconium oxide and zirconium silicate. 
     
     
       36. The semiconductor device according to claim 33, wherein:
 a thickness of said gate insulator film in said first transistors is about 5 nm, and   a thickness of said gate insulator film in said second transistors is about 2.5 nm.   
     
     
       37. The semiconductor device according to claim 33, wherein said first and second antenna ratios uses a sum of areas of exposed wires in a state that said exposed wires are conducted with a gate electrode in one of said first and second transistors during a manufacturing process of said device that generates charged particles. 
     
     
       38. The semiconductor device according to claim 37, comprising:
 determining said antenna ratio using a sum of top and side areas of said exposed wires.   
     
     
       39. The semiconductor device according to claim 37, comprising:
 determining said antenna ratio using a sum of top areas of said exposed wires.   
     
     
       40. The semiconductor device according to claim 37, wherein said sum of areas of exposed wires is defined as (wire width+2*1.3r)*total wire length, wherein said r is a thickness of a dielectric film deposited on said exposed wires. 
     
     
       41. The semiconductor device according to claim 16, comprising:
 a third circuit having third transistors with third wirings respectively connected to third gates of said third transistors, said third circuit having a third antenna ratio different than the first antenna ratio and different than the second antenna ratio,   wherein a thickness of a gate insulator film in said third transistors is thinner than a thickness of a gate insulator film in said second transistors, and   wherein the maximal value of said third antenna ratio of said third circuit is larger than the maximal value of said second antenna ratio of said second circuit.   
     
     
       42. The semiconductor device according to claim 41, wherein:
 a thickness of a gate insulator film in said first transistors is more than twice as thick as a thickness of a gate insulator film in said second transistors; and   a thickness of a gate insulator film in said second transistors is more than twice as thick as a thickness of a gate insulator film in said third transistors.   
     
     
       43. The semiconductor device according to claim 41, wherein:
 a thickness of said gate insulator film in said first transistors is about 5 nm;   a thickness of said gate insulator film in said second transistors is about 2.5 nm; and   a thickness of said gate insulator film in said third transistors is about 1 nm.   
     
     
       44. The semiconductor device according to claim 41, wherein;
 the maximal value of said second antenna ratio is made larger by at least one order of magnitude than the maximal value of said first antenna ratio; and   the maximal value of said third antenna ratio is made larger by at least one order of magnitude than the maximal value of said second antenna ratio.   
     
     
       45. The semiconductor device according to claim 44, wherein:
 a thickness of a gate insulator film in said first transistors is more than twice as thick as a thickness of a gate insulator film in said second transistors; and   a thickness of a gate insulator film in said second transistors is more than twice as thick as a thickness of a gate insulator film in said third transistors.