Transitioning from startup code to application code during initialization of a processor based device
Abstract
Method and apparatus for initializing a processor based device having a processor that controls an electrical load, such as a motor. The electrical load is initially operationally controlled using startup code executed by the processor. Processor control of the electrical load is next temporarily released so that the electrical load operates in an open control mode while the startup code is displaced with application code during a “brain transplant” operation. Processor operational control of the electrical load is thereafter resumed using the application code and the device is placed in an operational ready mode. The apparatus preferably comprises a data storage device and the electrical load preferably comprises a spindle motor configured to rotate a data storage medium on which the application code is stored, as well as an actuator motor which supports a data transducing head used to access the application code.
Claims
exact text as granted — not AI-modified1. A method, comprising:
controlling an electrical load with a first code executed by a processor;
releasing processor control so that the electrical load operates in an open control mode while the first code is displaced with a second code; and
reinstating processor control of the electrical load using the second code.
2. The method of claim 1 , wherein the first code of the controlling step is supplied from a boot read only memory (ROM).
3. The method of claim 1 , wherein the controlling step comprises loading the first code into a first memory location accessed by the processor.
4. The method of claim 3 , wherein the controlling step further comprises loading the second code into a second memory location accessible by the processor.
5. The method of claim 4 , wherein the releasing step comprises moving the second code from the second memory location into the first memory location, thereby displacing the first code from the first memory location.
6. The method of claim 1 , wherein the electrical load is a motor.
7. The method of claim 6 , wherein the motor supports a data storage medium, and wherein the controlling step comprises using the motor to rotate the data storage medium at an operational velocity and retrieving the second code from the rotating data storage medium.
8. The method of claim 1 wherein the processor operationally controls the electrical load.
9. The method of claim 1 , wherein at least one control signal is applied to the electrical load during the open control mode of the releasing step.
10. A method, comprising:
using a processor to execute startup code loaded into a memory location to initiate operational control of an electrical load;
continuing to operate the electrical load while processor operational control of the electrical load is temporarily suspended to load application code to the memory location; and
resuming operational control of the electrical load using the application code.
11. The method of claim 10 , wherein the startup code of the using step is supplied from a boot read only memory (ROM).
12. The method of claim 10 , wherein the memory location of the using step is characterized as a first memory location, and wherein the using step further comprises loading the application code into a second memory location accessible by the processor.
13. The method of claim 12 , wherein the continuing step comprises moving the application code from the second memory location into the first memory location, thereby displacing the startup code from the first memory location.
14. The method of claim 10 , wherein the electrical load comprises a motor supporting a data storage medium, and wherein the using step comprises energizing the motor to rotate the data storage medium at an operational velocity and retrieving the application code from the rotating data storage medium.
15. The method of claim 14 , wherein the using step further comprises using the startup code to energize an actuator motor to bring a data transducing head into alignment with a track defined on the data storage medium, and utilizing the head to transduce the application data from said track.
16. An apparatus, comprising:
an electrical load;
a memory location; and
a programmable processor coupled to the memory location and adapted to control the electrical load, wherein during an initialization process the processor executes startup code loaded into the memory location to initiate operational control of the load, temporarily releases operational control of the electrical load so that the electrical load continues to operate in an open control mode while application code is loaded to the memory location, and resumes operational control of the electrical load using the application code.
17. The apparatus of claim 16 , further comprising a boot read only memory (ROM) which stores the startup code, wherein the startup code is loaded from the boot ROM to the memory location for execution by the processor.
18. The apparatus of claim 16 , wherein the memory location of the using step is characterized as a first memory location, and wherein the apparatus further comprises a second memory location accessible by the processor and into which the processor loads the application code.
19. The apparatus of claim 16 , wherein the electrical load comprises a motor supporting a data storage medium, and wherein the execution of the startup code by the processor results in the energizing of the motor to rotate the data storage medium at an operational velocity.
20. The apparatus of claim 19 , further comprising an actuator motor coupled to a data transducing head, and wherein the execution of the startup code by the processor further results in the energizing of the actuator motor to bring the head into alignment with a track defined on the data storage medium, the head transducing the application data from said track.
21. A method, comprising:
measuring a parameter from a center tap node of an impedance element in an electrical circuit; providing power to the electrical circuit with the impedance element as a function of the parameter of the center tap node and an execution of a first application code by a processor; at least limiting execution of the first application code by the processor; providing, while execution of the first application code is at least limited, power to the impedance element as a function of the parameter of the center tap node; storing a second application code to be used in place of the first application code; and providing power to the electrical circuit with the impedance element as a function of the parameter and an execution of the second application code by the processor.
22. The method of claim 21, wherein the impedance element is an inductive element.
23. The method of claim 21, wherein the center tap node is located between at least two elements of the same impedance type and arranged in series and wherein the step of providing power includes providing a voltage across the two elements of the same impedance type.
24. The method of claim 21, further including the steps of monitoring current provided to the electrical circuit and limiting power provided to the impedance element in response to the monitored current.
25. The method of claim 21, wherein the first application code includes initialization steps for providing power to the impedance element, the initialization steps including
applying a first power-providing profile to the impedance element upon startup; detecting a property of the impedance element exceeding a threshold; applying, in response to the threshold having been exceeded, an intermediate power-providing profile to the impedance element; detecting that the property of the impedance element is approaching a final value; and maintaining, in response to the detection of the property of the impedance element approaching a final value, the detected property at the final value by controlling the current provided to the impedance element.
26. The method of claim 21, wherein the parameter measured from the center tap node is maintained within a predetermined tolerance.
27. A method comprising:
detecting an initial state of an impedance element of a storage device; applying, in response to the initial state, startup power to the impedance element of the storage device; modulating the applied startup power to limit current provided to the impedance element according to a current-limit value; detecting a parameter of the impedance element; and modifying the current-limit value in response to the detected parameter.
28. The method of claim 27, wherein the impedance element is an inductance.
29. The method of claim 27, further including the step of updating an application code that controls the modification of the current limit value.
30. The method of claim 27, further including the step of updating a first application code that controls the application of power to the storage device by
halting execution of the first application code; controlling power to the impedance element of the storage device in an open control mode while the execution of the first application code is halted; replacing the first application code with a second application code; and executing the second application code.
31. A storage device, comprising:
a non-volatile storage circuit; an electrical impedance circuit; a current sensor configured and arranged to sense current through the electrical impedance circuit; a control circuit configured and arranged to provide power to the electrical impedance circuit; and a programmable processor adapted to, during an initialization procedure, execute a first code that
receives an indication of sensed current from the current sensor, and
limits, in response to the sensed current, power provided by the control circuit,
after the initialization procedure,
apply power to the electrical impedance circuit by placing the control circuit into a closed control mode configured to maintain a parameter of the electrical impedance circuit,
place the control circuit into an open control mode for providing power to the electrical impedance circuit,
modify the first code, while the control circuit is in the open control mode, and
execute the modified first code.
32. The storage device of claim 31, wherein the electrical impedance circuit is an inductive circuit.
33. The storage device of claim 32, wherein the electrical impedance circuit includes two elements arranged in series.
34. The storage device of claim 32, wherein the electrical impedance circuit includes two elements arranged in series and a center tap representing a circuit node between the two elements, and wherein the programmable processor is further adapted to monitor a voltage on the center tap and to limit, in response to the monitored voltage on the center tap, power provided by the control circuit.Join the waitlist — get patent alerts
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