Interface circuits for modularized data optimization engines and methods therefor

Abstract

A data optimization engine for optimizing selected frames of a first stream of data. The data optimization engine includes a transmit interface circuit coupled to an optimization processor, the transmit interface circuit being configured for receiving the first stream of data. The transmit interface circuit includes a traffic controller circuit for separating frames in the first stream of data into a first optimizable frame and a first non-optimizable frame, and an optimization front-end circuit coupled to the traffic controller circuit to receive at least a first portion of the first optimizable frame. The optimization front-end circuit includes a protocol conversion circuit configured to convert data in the first portion of the first optimizable frame from a first protocol to a second protocol suitable for processing by the optimization processor, the first protocol specifies a first word length, the second protocol specifies a second word length different from the first word length. The optimization front-end circuit further includes an end-of-optimization-file processing circuit, the end-of-optimization-file processing circuit flagging an end of the first portion of the first optimizable frame to the optimization processor, wherein the optimization processor is configured to optimize the first portion of the first optimizable frame by performing at least one of compression and encryption on the first portion of the first optimizable frame.

1. A data optimization engine for optimizing selected frames of a first stream of data, comprising:
 a transmit interface circuit coupled to an optimization processor, said transmit interface circuit being configured for receiving said first stream of data, said transmit interface circuit includes
 a traffic controller circuit for separating frames in said first stream of data into a first optimizable frame and a first non-optimizable frame, and 
 an optimization front-end circuit coupled to said traffic controller circuit to receive at least a first portion of said first optimizable frame, said optimization front-end circuit including
 a protocol conversion circuit configured to convert data in said first portion of said first optimizable frame from a first protocol to a second protocol suitable for processing by said optimization processor, said first protocol specifies a first word length, said second protocol specifies a second word length different from said first word length, said optimization front-end circuit further includes 
 an end-of-optimization-file processing circuit, said end-of-optimization-file processing circuit flagging an end of said first portion of said first optimizable frame to said optimization processor, 
 wherein said optimization processor is configured to optimize said first portion of said first optimizable frame by performing at least one of compression and encryption on said first portion of said first optimizable frame. 
 
 
 
     
     
       2. The data optimization engine of  claim 1  wherein said end-of-optimization-file flagging processing circuit is configured to add, after said data in said first portion of said first optimizable frame is converted from said first protocol to said second protocol, an end-of-optimization-file flag to each word sent from said transmit interface circuit to said optimization processor. 
     
     
       3. The data optimization engine of  claim 2  wherein said end-of-optimization-file flag is one bit long. 
     
     
       4. The data optimization engine of  claim 1  wherein said first protocol is the 10-bit interface protocol, and said protocol conversion circuit includes a 10-bit/8-bit lookup table. 
     
     
       5. The data optimization engine of  claim 4  further including a frame alignment circuit for detecting and aligning a start of a primitive signal word in said first stream of data with a start of a reference 40-bit word, thereby framing said primitive signal word with respect to said reference 40-bit word. 
     
     
       6. The data optimization engine of  claim 5  wherein said frame alignment circuit detects said start of said primitive signal word by monitoring for a K28.5 10-bit word in said first stream of data. 
     
     
       7. The data optimization engine of  claim 4  further including an output FIFO coupled to said traffic controller circuit and said optimization front-end circuit, said traffic controller circuit further includes a start-of-frame handler circuit and an end-of-frame handler circuit, said start-of-frame handler circuit is configured detect a start-of-frame 40-bit word in said first optimizable frame and to send said start-of-frame 40-bit word to said output FIFO, effectively bypassing said optimization front-end circuit, said end-of-frame handler circuit is configured to detect an end-of-frame 40-bit word in said first optimizable frame and to temporarily retain said end-of-frame 40-bit word while waiting for said optimization processor to complete optimizing said first portion of said first optimizable frame, said end-of-frame handler circuit is further configured to furnish a polarity-correct version of said end-of-frame 40-bit word to said output FIFO for appending to first optimized data within said output FIFO, said first optimized data represents a first optimized version of said first portion of said first optimizable frame after being optimized by said optimization processor. 
     
     
       8. The data optimization engine of  claim 7  wherein said transmit interface circuit further includes an end-of-optimized-data flag handler circuit coupled to receive second optimized data from said optimization processor, said second optimized data represents a second optimized version of said first portion of said first optimizable frame after being optimized by said optimization processor, said end-of-optimized data flag handler being configured to detect an end-of-optimized data flag in said second optimized data and signals, upon detecting said end-of-optimized data flag in said second optimized data, said end-of-frame handler circuit to furnish said polarity-correct version of said end-of-frame 40-bit word to said output FIFO. 
     
     
       9. The data optimization engine of claim 1, wherein the data optimization engine is configured to be deployed in a Fiber Channel setting. 
     
     
       10. The data optimization engine of claim 1, wherein the data optimization engine is configured to be interposed between a Fiber Channel controller and a serializer/deserializer. 
     
     
       11. The data optimization engine of claim 1, wherein the data optimization engine is configured to work in conjunction with protocols selected from a group of protocols comprising: Ethernet protocols, Extended Attachment Unit Interface (XAUI) protocols, or I-SCSI protocols. 
     
     
       12. The data optimization engine of claim 1, wherein the data optimization engine is configured to be deployed between a host device and a storage device. 
     
     
       13. The data optimization engine of claim 12, wherein the data optimization engine is configured to be deployed between the host device and multiple different types of interfaces. 
     
     
       14. The data optimization engine of claim 13, wherein said multiple different types of interfaces comprise interfaces selected from a group of interfaces comprising at least: a Fiber Channel interface, an Ethernet interface, a SCSI interface and an Infiniband interface. 
     
     
       15. The data optimization engine of claim 1, wherein the data optimization engine is configured to be deployed between a CPU and a memory. 
     
     
       16. The data optimization engine of claim 1, wherein the data optimization engine is configured to be deployed between networked devices. 
     
     
       17. The data optimization engine of claim 16, wherein said networked devices comprise networked devices selected from a group of networked devices comprising: a network interface card, a router, or a switch. 
     
     
       18. The data optimization engine of claim 16, wherein a network associated with the networked devices is a network in which only routers and switches at an edge of the network perform compression/decompression and/or encryption/decryption. 
     
     
       19. The data optimization engine of claim 1, wherein the data optimization engine is configured to be interposed between two PCI devices. 
     
     
       20. The data optimization engine of claim 19, wherein the data optimization engine is configured to:
 process memory write transactions between the two PCI devices for possible encryption and/or compression; and   process memory read transactions between the two PCI devices for possible decryption and/or decompression.   
     
     
       21. A method comprising:
 receiving a stream of data;   separating frames in said stream of data into a first optimizable frame and a first non-optimizable frame;   converting data in a first portion of said first optimizable frame from a first protocol to a second protocol suitable for processing by an optimization processor, wherein said first protocol specifies a first word length and said second protocol specifies a second word length different from said first word length;   adding an indication to an end of said first portion of said first optimizable frame for the optimization processor; and   in response to said adding, performing, with said optimization processor, at least one of compression or encryption on said first portion of said first optimizable frame.   
     
     
       22. The method of claim 21, wherein said adding said indication comprises adding a flag indicating an end-of-optimization to a last word of said first portion of said first optimizable frame. 
     
     
       23. The method of claim 22, wherein said flag is one bit long. 
     
     
       24. The method of claim 21 wherein said first protocol is a 10-bit interface protocol, and said converting comprises using a 10-bit/8-bit lookup table. 
     
     
       25. The method of claim 24 further comprising detecting and aligning a start of a primitive signal word in said first stream of data with a start of a reference 40-bit word effective to frame said primitive signal word with respect to said reference 40-bit word. 
     
     
       26. The method of claim 25 wherein said detecting is performed by monitoring for a K28.5 10-bit word in said first stream of data. 
     
     
       27. The method of claim 24 further comprising:
 detecting a start-of-frame 40-bit word in said first optimizable frame and sending said start-of-frame 40-bit word to an output FIFO;   detecting an end-of-frame 40-bit word in said first optimizable frame and temporarily retaining said end-of-frame 40-bit word while waiting for completion of optimizing said first portion of said first optimizable frame; and   furnishing a polarity-correct version of said end-of-frame 40-bit word to said output FIFO for appending to first optimized data within said output FIFO, said first optimized data representing a first optimized version of said first portion of said first optimizable frame after being optimized by said optimization processor.   
     
     
       28. The method of claim 27 further comprising:
 receiving second optimized data from said optimization processor, said second optimized data representing a second optimized version of said first portion of said first optimizable frame after being optimized by said optimization processor;   detecting an end-of-optimized data flag in said second optimized data; and   upon detecting said end-of-optimized data flag in said second optimized data, furnishing said polarity-correct version of said end-of-frame 40-bit word to said output FIFO.   
     
     
       29. The method of claim 21, wherein each of the first and second protocols is one of an optical protocol, a wired protocol, or a wireless protocol, and wherein the first protocol is different from the second protocol. 
     
     
       30. The method of claim 21, wherein each of the first and second protocols is one of an Ethernet protocol, a Transmission Control Protocol (TCP), an Internet Protocol (IP), a TCP/IP protocol, a Fiber Channel Protocol (FCP), an Extended Attachment Unit Interface (XAUI) protocol, a Small Computer System Interface (SCSI) protocol, a storage over Ethernet (I-SCSI) protocol, a Peripheral Component Interconnect (PCI) protocol, an extended PCI (PCI-X) protocol, an Infiniband protocol, a High Speed Serial Interface (HSSI) protocol, a 10-bit interface (TBI) protocol, an Advanced Technology Attachment (ATA) protocol, an Integrated Drive Electronics (IDE) protocol, or a 64/66 protocol, and wherein the first protocol is different from the second protocol. 
     
     
       31. A system comprising:
 means for receiving a stream of data;   means for separating frames in said stream of data into a first optimizable frame and a first non-optimizable frame;   means for converting data in a first portion of said first optimizable frame from a first protocol to a second protocol suitable for processing by an optimization processor, wherein said first protocol specifies a first word length and said second protocol specifies a second word length different from said first word length;   means for adding an indication to an end of said first portion of said first optimizable frame for the optimization processor; and   means for performing, with said optimization processor and in response to said adding, at least one of compression or encryption on said first portion of said first optimizable frame.   
     
     
       32. The system of claim 31, wherein said means for adding said indication comprises means for adding a flag indicating an end-of-optimization to a last word of said first portion of said first optimizable frame. 
     
     
       33. The system of claim 32, wherein said flag is one bit long. 
     
     
       34. The system of claim 31 wherein said first protocol is a 10-bit interface protocol, and said means for converting comprises means for using a 10-bit/8-bit lookup table. 
     
     
       35. The system of claim 34 further comprising means for detecting and means for aligning a start of a primitive signal word in said first stream of data with a start of a reference 40-bit word effective to frame said primitive signal word with respect to said reference 40-bit word. 
     
     
       36. The system of claim 35 wherein said means for detecting comprises means for monitoring for a K28.5 10-bit word in said first stream of data. 
     
     
       37. The system of claim 34 further comprising:
 means for detecting a start-of-frame 40-bit word in said first optimizable frame and means for sending said start-of-frame 40-bit word to an output FIFO;   means for detecting an end-of-frame 40-bit word in said first optimizable frame and means for temporarily retaining said end-of-frame 40-bit word while waiting for completion of optimizing said first portion of said first optimizable frame; and   means for furnishing a polarity-correct version of said end-of-frame 40-bit word to said output FIFO for appending to first optimized data within said output FIFO, said first optimized data representing a first optimized version of said first portion of said first optimizable frame after being optimized by said optimization processor.   
     
     
       38. The system of claim 37 further comprising:
 means for receiving second optimized data from said optimization processor, said second optimized data representing a second optimized version of said first portion of said first optimizable frame after being optimized by said optimization processor;   means for detecting an end-of-optimized data flag in said second optimized data; and   means for furnishing said polarity-correct version of said end-of-frame 40-bit word to said output FIFO upon detecting said end-of-optimized data flag in said second optimized data.   
     
     
       39. A computing device comprising:
 a processor;
 one or more computer-readable storage devices; 
 a data optimization engine operably associated with the processor and the one or more computer-readable storage devices, the data optimization engine comprising: 
 a transmit interface circuit coupled to an optimization processor, said transmit interface circuit being configured for receiving a first stream of data, wherein said transmit interface circuit includes a traffic controller circuit for separating frames in said first stream of data into a first optimizable frame and a first nonoptimizable frame, and 
 an optimization front-end circuit coupled to said traffic controller circuit to receive at least a first portion of said first optimizable frame, said optimization front-end circuit including
 a protocol conversion circuit configured to convert data in said first portion of said first optimizable frame from a first protocol to a second protocol suitable for processing by said optimization processor, wherein said optimization front-end circuit further includes 
 an end-of-optimization-file processing circuit, said end-of-optimization-file processing circuit configured to flag an end of said first portion of said first optimizable frame to said optimization processor, 
 wherein said optimization processor is configured to optimize said first portion of said first optimizable frame by performing at least one of compression or encryption on said first portion of said first optimizable frame. 
 
   
     
     
       40. The computing device of claim 39 wherein said end-of-optimization-file processing circuit is configured to add, after said data in said first portion of said first optimizable frame is converted from said first protocol to said second protocol, an end-of-optimization-file flag to each word sent from said transmit interface circuit to said optimization processor. 
     
     
       41. The computing device of claim 40 wherein said end-of-optimization-file flag is one bit long. 
     
     
       42. The computing device of claim 39 wherein said first protocol is the 10-bit interface protocol, and said protocol conversion circuit includes a 10-bit/8-bit lookup table. 
     
     
       43. The computing device of claim 42 further including a frame alignment circuit for detecting and aligning a start of a primitive signal word in said first stream of data with a start of a reference 40-bit word, thereby framing said primitive signal word with respect to said reference 40-bit word. 
     
     
       44. The computing device of claim 43 wherein said frame alignment circuit is configured to detect said start of said primitive signal word by monitoring for a K28.5 10-bit word in said first stream of data. 
     
     
       45. The computing device of claim 42 further including an output FIFO coupled to said traffic controller circuit and said optimization front-end circuit, said traffic controller circuit further includes a start-of-frame handler circuit and an end-of-frame handler circuit, said start-of-frame handler circuit is configured detect a start-of-frame 40-bit word in said first optimizable frame and to send said start-of-frame 40-bit word to said output FIFO, effectively bypassing said optimization front-end circuit, said end-of-frame handler circuit is configured to detect an end-of-frame 40-bit word in said first optimizable frame and to temporarily retain said end-of-frame 40-bit word while waiting for said optimization processor to complete optimizing said first portion of said first optimizable frame, said end-of-frame handler circuit is further configured to furnish a polarity-correct version of said end-of-frame 40-bit word to said output FIFO for appending to first optimized data within said output FIFO, said first optimized data represents a first optimized version of said first portion of said first optimizable frame after being optimized by said optimization processor. 
     
     
       46. The computing device of claim 45 wherein said transmit interface circuit further includes an end-of-optimized-data flag handler circuit coupled to receive second optimized data from said optimization processor, said second optimized data represents a second optimized version of said first portion of said first optimizable frame after being optimized by said optimization processor, said end-of-optimized data flag handler being configured to detect an end-of-optimized data flag in said second optimized data and signals, upon detecting said end-of-optimized data flag in said second optimized data, said end-of-frame handler circuit to furnish said polarity-correct version of said end-of-frame 40-bit word to said output FIFO. 
     
     
       47. The computing device of claim 39, wherein the data optimization engine is configured to be deployed in a Fiber Channel setting. 
     
     
       48. The computing device of claim 39, wherein the data optimization engine is configured to be interposed between a Fiber Channel controller and a serializer/deserializer. 
     
     
       49. The computing device of claim 39, wherein the data optimization engine is configured to work in conjunction with protocols selected from a group of protocols comprising: Ethernet protocols, Extended Attachment Unit Interface (XAUI) protocols, or I-SCSI protocols. 
     
     
       50. The computing device of claim 39, wherein the data optimization engine is configured to be deployed between a host device and a storage device. 
     
     
       51. The computing device of claim 50, wherein the data optimization engine is configured to be deployed between the host device and multiple different types of interfaces. 
     
     
       52. The computing device of claim 51, wherein said multiple different types of interfaces comprise interfaces selected from a group of interfaces comprising: a Fiber Channel interface, an Ethernet interface, a SCSI interface and an Infiniband interface. 
     
     
       53. The computing device of claim 39, wherein the data optimization engine is configured to be deployed between a CPU and a memory. 
     
     
       54. The computing device of claim 39, wherein the data optimization engine is configured to be deployed between networked devices. 
     
     
       55. The computing device of claim 54, wherein said networked devices comprise networked devices selected from a group of networked devices comprising: a network interface card, a router, or a switch. 
     
     
       56. The computing device of claim 39, wherein the data optimization engine is configured to be interposed between two PCI devices. 
     
     
       57. The computing device of claim 56, wherein the data optimization engine is configured to:
 process memory write transactions between the two PCI devices for possible encryption and/or compression; and   process memory read transactions between the two PCI devices for possible decryption and/or decompression.