Stackable layer containing ball grid array package

Abstract

Layers suitable for stacking in three dimensional, multilayer modules are formed by interconnecting a ball grid array electronic package to an interposer layer which routes electronic signals to an access plane. The layers are underfilled and may be bonded together to form a stack of layers. The leads on the access plane are interconnected among layers to form a high-density electronic package.

1. A stackable layer comprised of:
 a BGA package comprising at least one I/O terminal on the underside thereof, 
 an interposer layer bonded to said underside and having at least one electrically conductive trace disposed thereon in electrical connection with said at least one I/O terminal, 
 wherein said BGA package and said interposer layer each have a lateral surface substantially coplanar with an access plane, 
 said at least one electrically conductive trace terminating at said access plane to define an access lead, a metallized conductive trace defined on said lateral surface of said BGA package and on said interposer layer, 
 said metallized conductive trace in electrical connection with said access lead and in electrical connection with external electronic circuitry. 
 
     
     
       2. The stackable layer of  claim 1  wherein said metallized conductive trace is defined using a laser ablation process. 
     
     
       3. The stackable layer of  claim 1  wherein said metallized conductive trace is defined using a photolithographic plating process. 
     
     
       4. The stackable layer of  claim 1  wherein said metallized conductive trace is defined using a mechanical saw-cutting process. 
     
     
       5. A stackable layer comprising:
 an integrated circuit (IC) package including an input/output (I/O) terminal;   an interposer layer bonded to the IC package and including a first electrically conductive trace electrically connected to the I/O terminal, wherein a first surface of the IC package and a second surface of the interposer layer form a lateral surface, and wherein the first electrically conductive trace terminates at the lateral surface to define an access lead; and   a second electrically conductive trace on the lateral surface, wherein the second electrically conductive trace is electrically connected to the access lead.   
     
     
       6. The stackable layer of claim 5, wherein the first electrically conductive trace is further electrically connected to a solder ball pad that is configured to electrically connect to the I/O terminal. 
     
     
       7. The stackable layer of claim 6, wherein the I/O terminal comprises a solder ball. 
     
     
       8. The stackable layer of claim 7, wherein the I/O terminal is electrically connected to the solder ball pad by a solder-reflow process. 
     
     
       9. The stackable layer of claim 5, wherein the stackable layer is encapsulated by an encapsulant. 
     
     
       10. The stackable layer of claim 5, further comprising an underfill between the IC package and the interposer layer. 
     
     
       11. The stackable layer of claim 5, further comprising a plurality of conductive traces configured to electrically connect a plurality of I/O terminals of the IC package to a plurality of access leads on the lateral surface. 
     
     
       12. The stackable layer of claim 5, wherein the IC package is a ball grid array (BGA) package. 
     
     
       13. A method comprising:
 bonding an integrated circuit (IC) package to an interposer layer;   electrically connecting an input/output (I/O) terminal disposed on the IC package to a first electrically conductive trace disposed on the interposer layer, wherein a first surface of the IC package and a second surface of the interposer layer form a lateral surface, and wherein the first electrically conductive trace terminates at the lateral surface to define an access lead; and   electrically connecting a second electrically conductive trace on the lateral surface to the access lead.   
     
     
       14. The method of claim 13, wherein the first electrically conductive trace is electrically connected to a solder ball pad that is configured to electrically connect to the I/O terminal. 
     
     
       15. The method of claim 14, wherein said electrically connecting an I/O terminal comprises:
 aligning the solder ball pad with the I/O terminal; and   electrically connecting the I/O terminal to the solder ball pad via a solder-reflow process.   
     
     
       16. The method of claim 13, further comprising encapsulating the IC package and the interposer layer in an encapsulant. 
     
     
       17. The method of claim 13, further comprising depositing an underfill between the IC package and the interposer layer. 
     
     
       18. The method of claim 13, further comprising electrically connecting a plurality of conductive traces on the lateral surface to a plurality of access leads for the interposer layer. 
     
     
       19. The method of claim 13, wherein the IC package is a ball grid array (BGA) package. 
     
     
       20. A stack of electronic layers comprising:
 a first layer including:
 a first integrated circuit (IC) package comprising a first input/output (I/O) terminal; 
 a first interposer layer bonded to the first IC package and comprising a first electrically conductive trace electrically connected to the first I/O terminal for the first IC package, wherein a first surface of the first IC package and a second surface of the first interposer layer form a first lateral surface, and wherein the first electrically conductive trace terminates at the first lateral surface to define a first access lead; and 
 a second electrically conductive trace on the first lateral surface, wherein the second electrically conductive trace is electrically connected to the first access lead; and 
   a second layer adhered to the first layer and including:
 a second IC package comprising a second I/O terminal; 
 a second interposer layer bonded to the second IC package and comprising a third electrically conductive trace electrically connected to the second I/O terminal of the second IC package, wherein a third surface of the second IC package and a fourth surface of the second interposer layer form a second lateral surface aligned with the first lateral surface, and wherein the third electrically conductive trace terminates at the second lateral surface to define a second access lead; and 
 a fourth electrically conductive trace on the second lateral surface, wherein the fourth electrically conductive trace is electrically connected to the second access lead. 
   
     
     
       21. The stack of claim 20, wherein at least one of the first or second electrically conductive traces is electrically connected to a solder ball pad that is configured to electrically connect to at least one of the first or second I/O terminals. 
     
     
       22. The stack of claim 20, wherein at least one of the first or second I/O terminals comprises a solder ball. 
     
     
       23. The stack of claim 20, wherein the stack is encapsulated by an encapsulant. 
     
     
       24. The stack of claim 20, further comprising an underfill between at least one of the first IC package and the first interposer layer or the second IC package and the second interposer layer. 
     
     
       25. The stack of claim 20, further comprising a plurality of electrically conductive traces configured to electrically connect a plurality of I/O terminals of the first and second IC packages to a plurality of access leads on the first and second lateral surfaces. 
     
     
       26. The stack of claim 20, wherein at least one of the first or second IC packages is a ball grid array (BGA) package. 
     
     
       27. A method comprising:
 bonding a first integrated circuit (IC) package to a first interposer layer to form a first stackable layer;   electrically connecting a first input/output (I/O) terminal disposed on the first IC package to a first electrically conductive trace disposed on the first interposer layer, wherein a first surface of the first IC package and a second surface of the first interposer layer form a first lateral surface, and wherein the first electrically conductive trace terminates at the first lateral surface to define a first access lead;   electrically connecting a second electrically conductive trace on the first lateral surface to the first access lead;   bonding a second IC package to a second interposer layer to form a second stackable layer;   electrically connecting a second I/O terminal disposed on the second IC package to a third electrically conductive trace disposed on the second interposer layer, wherein a first surface of the second IC package and a second surface of the second interposer layer form a second lateral surface aligned with the first lateral surface, and wherein the third electrically conductive trace terminates at the second lateral surface to define a second access lead;   electrically connecting a fourth electrically conductive trace on the second lateral surface to the second access lead and to the second electrically conductive trace; and   adhering the first stackable layer to the second stackable layer to form a stack.   
     
     
       28. The method of claim 27, wherein at least one of the first or second electrically conductive traces is electrically connected to a solder ball pad that is configured to electrically connect to at least one of the first or second I/O terminals. 
     
     
       29. The method of claim 28, wherein said electrically connecting a first I/O terminal comprises:
 aligning the solder ball pad with the first I/O terminal; and   electrically connecting the first I/O terminal to the solder ball pad via a solder-reflow process.   
     
     
       30. The method of claim 27, further comprising encapsulating the stack in an encapsulant. 
     
     
       31. The method of claim 27, further comprising disposing an underfill between at least one of the first IC package and the first interposer layer or the second IC package and the second interposer layer. 
     
     
       32. The method of claim 27, further comprising electrically connecting a plurality of electrically conductive traces on the first or second lateral surfaces to a plurality of access leads for the first or second interposer layers. 
     
     
       33. The method of claim 27, wherein at least one of the first or second IC packages is a ball grid array (BGA) package. 
     
     
       34. The method of claim 13, further comprising grinding the lateral surface to expose the access lead. 
     
     
       35. The method of claim 27, further comprising grinding at least one of the first or second lateral surfaces to expose at least one of the first or second access leads.