System and method for joint source-channel encoding, with symbol, decoding and error correction

Abstract

Disclosed is aA system and method for joint source-channel encoding, symbol decoding and error correction, preferably utilizing an arithmetic encoder with operational error detection space; and a combination sequential, and arithmetic, encoded symbol decoder structure.

We claim: 
     
       1. A variable length symbol, joint source-channel encoding, symbol decoding and error correction system comprising:
 encoder system; 
 modulation-transmission means; and 
 combination sequential, and encoded symbol, decoding systems; 
 
       said encoder system comprising input means for accepting a sequential plurality of allowed input symbols and output means for outputting an encoded sequence of bits for allowed symbols input thereinto; 
       said encoder system being functionally interconnected to said modulation-transmission means such that entry of a symbol to said encoder system results in said encoder means outputting an encoded sequence of bits therefore into said modulation-transmission means; 
       said modulation-transmission means and combination sequential, and encoded symbol, decoding systems being functionally interconnected such that an encoded symbol sequence of bits entered to said modulation-transmission means enters said combination sequential, and encoded symbol, decoding systems; 
       said sequential decoding system comprising a plurality of bistable elements; 
       said encoded symbol decoding system comprising means for initiating an error correction routine to the end that, upon the detecting of the presence of an unexpected encoded reserved symbol a selection from the group consisting of:
 at least one bistable element in said sequential decoding means is changed; and 
 selection is made of a series of sequential bits, said selection being made from a group consisting of a plurality of such series of sequential bits which result from the changing of bistable elements in said sequential decoder means; 
 
       is performed; 
       wherein said reserved symbol is not allowed as an input symbol to said symbol encoder system input means, and wherein the detection of the presence of an encoded allowed symbol by said encoded symbol decoding system does not initiate said error correction routine. 
     
     
       2. A variable length symbol joint source-channel encoding, symbol decoding and error correction system comprising:
 encoder means; 
 modulation-transmission means; and 
 combination sequential, and encoded symbol, decoding means; 
 
       said encoder means comprising input means for accepting a sequential plurality of allowed input symbols and output means for outputting an encoded sequence of bits for allowed symbols input thereinto; 
       said encoder means further having means for generating, and in a sequence expected by said encoded symbol decoding means, outputting an encoded sequence of bits for at least one reserved symbol before and/or after an encoded allowed input symbol, which reserved symbol is not allowed as an input symbol to said encoder means input means; 
       said encoder means being functionally interconnected to said modulation-transmission means such that entry of a symbol to said encoder means results in said encoder means outputting an encoded sequence of bits therefore into said modulation-transmission means; 
       said modulation-transmission means and combination sequential, and encoded symbol, decoding means being functionally interconnected such that an encoded symbol sequence of bits entered to said modulation-transmission means enters said encoded symbol decoding means; 
       said sequential decoding means comprising a plurality of bistable elements; 
       said encoded symbol decoding means comprising means for initiating an error correction routine to the end that, upon the detecting of the presence of an unexpected encoded reserved symbol, or the absence of an expected encoded sequence of bits for a reserved symbol, a selection from the group consisting of:
 at least one bistable element in said sequential decoding 
 means is changed; and 
 selection is made of a series of sequential bits, said selection being made from a group consisting of a plurality of such series of sequential bits which result from the changing of bistable elements in said sequential decoder means; 
 
       is performed; 
       and wherein the detection of the presence of an encoded allowed symbol, other than by its coincidental presence in the place of an absent expected reserved symbol, by said encoded symbol decoding means, does not initiate said error correction routine. 
     
     
       3. A joint source-channel encoding, symbol decoding and error correction system comprising:
 encoder means; 
 modulation-transmission means; and 
 decoding means; 
 
       wherein said encoder means comprises input means for accepting a sequential plurality of allowed input symbols and output means for outputting an encoded sequence of bits for allowed symbols input thereinto; 
       wherein said decoding means comprises a functional combination of a sequential decoder means which comprises a sequence of bistable elements, each of which can be set to represent encoded symbol bits, and an encoded symbol decoder means; 
       said encoder means being functionally interconnected to said modulation-transmission means and said modulation-transmission means being functionally interconnected to said decoding means; 
       such that in use said encoder means receives a sequence of allowed symbols at its input means and provides an encoded sequence of bits for at least some thereof, said sequence of bits being caused to arrive at said decoding means; 
       and said encoded symbol decoder means having error detection means such that in use said encoded symbol decoder means, upon detecting the presence of an unexpected encoded sequence of bits for reserved symbol, initiates an error correction routine to the end that a selection from the group consisting of:
 at least one bistable element in said sequential encoding decoder means is changed; and 
 selection is made of a series of sequential bits, said selection being made from a group consisting of aplurality of such series of sequential bits which result from the changing of bistable elements in said sequential decoder means; 
 
       is performed; 
       wherein said reserved symbol is not allowed as an input symbol to said encoder means input means, and wherein the detecting of the presence of an encoded allowed symbol by said decoding means does not initiate said error correction routine. 
     
     
       4. A joint source-channel encoding, symbol decoding and error correction system as in  claim 3  in which said encoder means is an arithmetic encoder and said decoding means comprises, as the encoded symbol decoder means, an arithmetic decoder. 
     
     
       5. A joint source-channel encoding, symbol decoding and error correction system comprising:
 encoder means; 
 modulation-transmission means; and 
 decoding means; 
 
       wherein said decoding means comprises a functional combination of a sequential decoder means which comprises a sequence of bistable elements, each of which can be set to represent encoded symbol bits, and an encoded symbol decoder means; 
       wherein said encoder means comprises input means for accepting a sequential plurality of allowed input symbols and output means for outputting an encoded sequence of bits for allowed symbols input thereinto, said encoder means further having means for generating and, in a sequence expected by said encoded symbol decoder means, outputting an encoded sequence of bits for at least one reserved symbol before and/or after an encoded allowed input symbol, which reserved symbol is not allowed as an input symbol to said encoder means input means; 
       said encoder means being functionally interconnected to said modulation-transmission means and said modulation-transmission means being functionally interconnected to said decoding means; 
       such that in use said encoder means receives a sequence of allowed symbols at its input means and provides an encoded sequence of bits for at least some thereof in optional combination with a sequence of bits which represent at least one encoded reserved symbol in a pattern expected by said decoder means, said sequence of bits being caused to arrive at said decoding means; 
       and said encoded symbol decoder means having error detection means such that in use said encoded symbol decoder means, upon detecting the absence of an expected encoded reserved symbol, or the presence of an unexpected encoded reserved symbol, initiates an error correction routine to the end that a selection from the group consisting of:
 at least one bistable element in said sequential decoding means is changed; and 
 selection is made of a series of sequential bits, said selection being made from a group consisting of a plurality of such series of sequential bits which result from the changing of bistable elements in said sequential decoder means; 
 
       is performed; 
       and wherein the detection of the presence of an encoded allowed symbol, other than by its coincidental presence in the place of an absent expected reserved symbol, by said decoding means, does not initiate said error correction routine. 
     
     
       6. A joint source-channel encoding, symbol decoding and error correction system as in  claim 5  in which said encoder means is an arithmetic encoder and said decoding means comprises, as the encoded symbol decoder means, an arithmetic decoder. 
     
     
       7. A joint source-channel encoding, symbol decoding and error correction system comprising:
 arithmetic encoder system; 
 modulation-transmission means; and 
 decoding system; 
 
       wherein said arithmetic encoder system comprises input means for accepting a sequential plurality of allowed input symbols and output means for outputting an encoded sequence of bits for allowed symbols input therein to; 
       wherein said decoding system comprises a functional combination of a sequential decoder system which comprises a sequence of bistable elements, each of which can be set to represent encoded symbol bits, and an arithmetic decoder system; 
       said arithmetic encoder system being functionally interconnected to said modulation-transmission means and said modulation-transmission means being functionally interconnected to said decoding system; 
       such that in use said arithmetic encoder system receives a sequence of allowed symbols at its input means and provides an encoded sequence of bits for at least some thereof, said sequence of bits being caused to arrive at said decoding system; 
       and said arithmetic decoder system having error detection means such that in use said arithmetic decoder system, upon detecting the presence of an unexpected encoded reserved symbol, initiates an error correction routine to the end that a selection from the group, consisting of:
 at least one bistable element in said sequential encoding means decoder system is changed; and 
 selection is made of a series of sequential bits, said selection being made from a group consisting of a plurality of such series of sequential bits which result from the changing of bistable elements in said sequential decoder means decoder system; 
 
       is performed; 
       wherein said reserved symbol is not allowed as an input symbol to said arithmetic encoder system input means, and wherein the detecting of the presence of an encoded allowed symbol by said decoding system does not initiate said error correction routine. 
     
     
       8. A joint source-channel encoding, symbol decoding and error correction system comprising:
 arithmetic encoder means; 
 modulation-transmission means; an 
 decoding means; 
 
       wherein said decoding means comprises a functional combination of a sequential decoder means which comprises a sequence of bistable elements, each of which can be set to represent encoded symbol bits, and an arithmetic decoder means; 
       wherein said arithmetic encoder means comprises input means for accepting a sequential plurality of allowed input symbols and output means for outputting an encoded sequence of bits for allowed symbols input thereinto, said arithmetic encoder means further having means for generating and, in a sequence expected by said arithmetic decoder means, outputting an encoded sequence of bits for at least one reserved symbol before and/or after an encoded allowed input symbol, which reserved symbol is not allowed as an input symbol to said arithmetic encoder means input means; 
       said arithmetic encoder means being functionally interconnected to said modulation-transmission means and said modulation-transmission means being functionally interconnected to said decoding means; 
       such that in use said arithmetic encoder means receives a sequence of allowed symbols at its input means and provides an encoded sequence of bits for at least some thereof in optional combination with at least one encoded reserved symbol in a pattern expected by said arithmetic decoder means, said sequence of bits being caused to arrive at said decoding means; 
       and said arithmetic decoder means having error detection means such that in use said arithmetic decoder means, upon detecting the absence of an expected encoded reserved symbol, or the presence of an unexpected encoded reserved symbol, initiates an error correction routine to the end that a selection from the group consisting of:
 at least one bistable element in said sequential decoding means is changed; and 
 selection is made of a series of sequential bits, said selection being made from a group consisting of a plurality of such series of sequential bits which result from the changing of bistable elements in said sequential decoder means; 
 
       is performed; 
       and wherein the detection of the presence of an encoded allowed symbol, other than by its coincidental presence in the place of an absent expected reserved symbol, by said decoding means, does not initiate said error correction routine. 
     
     
       9. A method of correcting errors in decoded symbols which are encoded by an encoder means in a joint source-channel coding system, comprising the steps of:
 a. providing a joint source-channel encoding, symbol decoding and error correction system comprising:
 encoder means; 
 modulation-transmission means; and 
 decoding means; 
 
 
       wherein said decoding means comprises a functional combination of a sequential decoder means which comprises a sequence of bistable elements, each of which can be set to represent encoded symbol bits, and an encoded symbol decoder means; 
       wherein said encoder means comprises input means for accepting a sequential plurality of allowed input symbols and output means for outputting an encoded sequence of bits for allowed symbols input thereinto, said encoder means further having means for generating and, in a sequence expected by said encoded symbol decoder means, outputting an encoded sequence of bits for at least one reserved symbol before and/or after an encoded allowed input symbol, which reserved symbol is not allowed as an input symbol to said encoder means input means; 
       said encoder means being functionally interconnected to said modulation-transmission means and said modulation-transmission means being functionally interconnected to said decoding means; 
       such that in use said encoder means receives a sequence of allowed symbols at its input means and provides an encoded sequence of bits for at least some thereof, in optional combination with at least one encoded reserved symbol in a pattern expected by said decoder means, said sequence of bits being caused to arrive at said decoding means; 
       and said encoded symbol decoder means having error detection means such that in use said encoded symbol decoder means, upon detecting the absence of an expected encoded reserved symbol, or the presence of an unexpected encoded reserved symbol, initiates an error correction routine to the end that a selection from the group consisting of:
 at least one bistable element in said sequential decoding means is changed; and 
 selection is made of a series of sequential bits, said selection being made from a group consisting of a plurality of such series of sequential bits which result from the changing of bistable elements in said sequential decoder means; 
 
       is performed; 
       wherein the detection of the presence of an encoded allowed symbol, other than by its coincidental presence in th place of an absent expected reserved symbol, by said decoding means, does not initiate said error correction routine;
 b. inputting a plurality of symbols to the input means of said encoder means; 
 c. causing said encoder means to encode at least some of said plurality of symbols and output bits corresponding thereto into said modulation-transmission means; 
 d. causing said modulation-transmission means to enter said at least some of said plurality of encoded symbols into said functional combination of said sequential decoder means and encoded symbol decoder means; 
 e. causing said encoded symbol decoder means to, if detecting a present unexpected or absent expected, encoded reserved symbol, perform a selection from the group consisting of:
 change at least one bistable element in said sequential decoder means; and 
 select a series of sequential bits, said selection being made from a group consisting of a plurality of such series of sequential bits which result from the changing of bistable elements in said sequential decoder means. 
 
 
     
     
       10. A method as in  claim 9 , wherein said encoded reserved symbol is selected from a group of at least two reserved symbols, and wherein at least two different expected reserve symbols are selected and entered into said modulation-transmission means. 
     
     
       11. A method of correcting errors in decoded symbols which are encoded by an arithmetic encoder in a joint source-channel coding system, comprising the steps of:
 a. providing a joint source-channel encoding, symbol decoding and error correction system comprising:
 arithmetic encoder means; 
 modulation-transmission means; and 
 decoding means; 
 
 
       wherein said arithmetic encoder means comprises input means for accepting a sequential plurality of allowed input symbols and output means for outputting an encoded sequence of bits for allowed symbols input thereinto; 
       wherein said decoding means comprises a functional combination of a sequential decoder means which comprises a sequence of bistable elements, each of which can be set to represent encoded symbol bits, and an arithmetic decoder means; 
       said arithmetic encoder means being functionally interconnected to said modulation-transmission means and said modulation-transmission means being functionally interconnected to said decoding means; 
       such that in use said arithmetic encoder means receives a sequence of allowed symbols at its input means and provides an encoded sequence of bits for at least some thereof, said sequence of bits being caused to arrive at said decoding means; 
       and said arithmetic decoder means having error detection means such that in use said arithmetic decoder means, upon detecting the presence of an unexpected encoded reserved symbol, initiates an error correction routine to the end that a selection from the group consisting of:
 at least one bistable element in said sequential decoding means is changed; and 
 selection is made of a series of sequential bits, said selection being made from a group consisting of a plurality of such series of sequential bits which result from the changing of bistable elements in said sequential decoder means; 
 
       is performed; 
       wherein said reserved symbol is not allowed as an input symbol to said arithmetic encoder means input means, and wherein the detection of the presence of an allowed encoded symbol by said decoding means does not initiate said error correction routine;
 b. inputting a plurality of symbols to the input means of said arithmetic encoder means; 
 c. causing said arithmetic encoder means to encode at least some of said plurality of symbols and output bits corresponding thereto into said modulation-transmission means; 
 d. causing said modulation-transmission means to enter said at least some of said plurality of encoded symbols into said functional combination of said sequential decoder means and arithmetic decoder means; 
 e. causing said arithmetic decoder means to, if detecting a present unexpected encoded reserved symbol perform a selection from the group consisting of:
 change at least one bistable element in said sequential decoder means; and 
 select a series of sequential bits, said selection being made from a group consisting of a plurality of such series of sequential bits which result from the changing of bistable elements in said sequential decoder means. 
 
 
     
     
       12. A method as in  claim 11 , wherein said encoded reserved symbol is selected from a group of at least two reserved symbols. 
     
     
       13. A method of correcting errors in decoded symbols which are encoded by an arithmetic encoder in a joint source-channel coding system, comprising the steps of:
 a. providing a joint source-channel encoding, symbol decoding and error correction system comprising:
 arithmetic encoder means; 
 modulation-transmission means; and 
 decoding means; 
 
 
       wherein said decoding means comprises a functional combination of a sequential decoder means which comprises a sequence of bistable elements, each of which can be set to represent encoded symbol bits, and an arithmetic decoder means; 
       wherein said arithmetic encoder means comprises input means for accepting a sequential plurality of allowed input symbols and output means for outputting an encoded sequence of bits for allowed symbols input thereinto, said arithmetic encoder means further having means for generating and, in a sequence expected by said arithmetic decoder means, outputting an encoded sequence of bits for at least one reserved symbol before and/or after an allowed input symbol, which reserved symbol is not allowed as an input symbol to said arithmetic encoder means input means; 
       said arithmetic encoder means being functionally interconnected to said modulation-transmission means and said modulation-transmission means being functionally interconnected to said decoding means; 
       such that in use said arithmetic encoder means receives a sequence of allowed symbols at its input means and provides an encoded sequence of bits for at least some thereof in optional combination with at least one encoded reserved symbol in a pattern expected by said arithmetic decoder means, said sequence of bits being caused to arrive at said decoding means; 
       and said arithmetic decoder means having error detection means such that in use said arithmetic decoder means, upon detecting the absence of an expected encoded reserved symbol, or the presence of an unexpected encoded reserved symbol, initiates an error correction routine to the end that a selection from the group consisting of:
 at least one bistable element in said sequential decoding means is changed; and 
 selection is made of a series of sequential bits, said selection being made from a group consisting of a plurality of such series of sequential bits which result from the changing of bistable elements in said sequential decoder means; 
 
       is performed; 
       wherein said reserved symbol is not allowed as an input symbol to said arithmetic encoder means input means and wherein the detection of the presence of an allowed symbol, other than by its coincidental presence in the place of an absent expected encoded reserved symbol, by said decoding means, does not initiate said error correction routine;
 b. inputting a plurality of symbols to the input means of said arithmetic encoder means; 
 c. causing said arithmetic encoder means to encode at least some of said plurality of symbols and output bits corresponding thereto, optionally intermingled with arithmetic at least one encoder means generated reserved symbol, into said modulation-transmission means; 
 d. causing said modulation-transmission means to enter said at least some of said plurality of encoded symbols, optionally along with at least one encoded reserved symbol entered into said modulation-transmission means, into said functional combination of said sequential decoder means and arithmetic decoder means; 
 e. causing said arithmetic decoder means to, if detecting a non-present expected or present unexpected encoded reserved symbol, perform a selection from the group consisting of:
 change at least one bistable element in said sequential decoder means; and 
 select a series of sequential bits, said selection being made from a group consisting of a plurality of such series of sequential bits which result from the changing of bistable elements in said sequential decoder means. 
 
 
     
     
       14. A method as in  claim 13 , wherein said encoded reserved symbol is selected from a group of at least two reserved symbols, and wherein at least two different expected reserve symbols are selected and entered into said modulation-transmission means. 
     
     
       15. A method of correcting errors in decoded symbols which are encoded by an arithmetic encoder in a joint source-channel coding system, comprises the steps of:
 a. providing a joint source-channel encoding, symbol decoding and error correction, system comprising:
 arithmetic encoder means; 
 modulation-transmission means; and 
 decoding means; 
 
 
       wherein said decoding means comprises a functional combination of a sequential decoder means which comprises a sequence of bistable elements, each of which can be set to represent encoded symbol bits, and an arithmetic decoder means; 
       wherein said arithmetic encoder means comprises input means for accepting a sequential plurality of allowed input symbols and output means for outputting an encoded sequence of bits for allowed symbols input thereinto, said arithmetic encoder means further having means for generating and, in a sequence expected by said arithmetic decoder means, outputting an encoded sequence of bits for at least one reserved symbol before and/or after an encoded allowed input symbol, which reserved symbol is not allowed as an input symbol to said arithmetic encoder means input means; 
       said arithmetic encoder means being functionally interconnected to said modulation-transmission means and said modulation-transmission means being functionally interconnected to said decoding means; 
       such that in use said arithmetic encoder means receives a sequence of allowed symbols at its input means and provides an encoded sequence of bits for at least some thereof in optional combination with at least one encoded reserved symbol in a pattern expected by said arithmetic decoder means, said sequence of bits being caused to arrive at said decoding means; 
       and said arithmetic decoder means having error detection means such that in use said arithmetic decoder means, upon detecting the absence of an expected encoded reserved symbol, or the presence of an unexpected encoded reserved symbol, initiates an error correction routine to the end that at least one bistable element in said sequential decoder means is changed;
 b. entering a sequence of symbols into said arithmetic encoder such that said sequence of symbols are encoded and exited therefrom as a binary bit stream sequence of + x  √{square root over (E 8 )} and − x  √{square root over (E 8 )} signals, corresponding to a string of “1”/(“0”)'s and “0”/(“1”)'s which pass through said transmission channel and enter said sequential decoder means, where  x  is a fraction; 
 c. making hard logic circuitry decisions as to the presence of “1”/(“0”)'s and “0”/(“1”)'s based on said binary bit stream sequence of + x √{square root over (E s )} and − x √{square root over (E s )} signals while identify decisions based upon signals wherein  x  is of a value so as to cause the values of + x √{square root over (E s )} or − x √{square root over (E s )} to be within a null zone of +Δ to −Δ around 0,0, and identifying said decisions as “branch point”, decisions in said sequential decoder means; 
 d. monitoring output from said arithmetic decoder for errors and when if an error is indicated thereby, identifying a “branch point” in said sequential decoder means and correcting the “1”/(“0”) or “0”/(“1”) based binary bit thereat by inverting it to “0”/(“1”) or “1”/(“0”). 
 
     
     
       16. A method of correcting errors in decoded symbols as in  claim 15 , in which in step d. involves the determination of the presence or absence of non-alphabet symbols other than as expected, said non-alphabet symbols being not-allowed as arithmetic encoder input symbols. 
     
     
       17. A method of correcting errors in decoded symbols as in  claim 15 , which comprises practicing step d. more than once, with said error correcting method further comprising the step of:
 e. defining a tolerable Hamming distance threshold Tc, and keeping count of the number Kc of “branch points” in said sequential decoder means at which correction of the “1”/(“0”) or “0”/(“1”) based binary bit thereat by inverting to “0”/(“1”) or “1”/(“0”) has been performed; and
 if Kc exceeds Tc, expanding the null zone by increasing the magnitude of Δ, thereby making available additional “branch points”. 
 
 
     
     
       18. A method of correcting errors in decoded symbols as in  claim 17 , said error correction method of further comprising the step of:
 f. determining in a second or greater practice of step e. if the identified “branch point” is sequentially prior to the “branch point” identified in the immediately previous practice of step e. and if so decreasing the value of Kc by 1, otherwise increasing the value of Kc by 1. 
 
     
     
       19. A method of correcting errors in decoded symbols as in  claim 15 , which comprises practicing step d. more than once, with said error correcting method further comprising the step of:
 e. defining a means for calculating a Euclidean distance between received and decoded symbols, and a tolerable rate of increase of Euclidean distance between sequential practice of step d., and
 if said Euclidean distance increases faster than at said tolerable rate, expanding the null zone by increasing he magnitude of Δ, thereby making available additional “branch points”. 
 
 
     
     
       20. A method of correcting errors in decoded symbols which are encoded by an arithmetic encoder in a joint source-channel coding system, comprises the step of:
 a. providing a joint source-channel encoding, symbol decoding and error correction system comprising:
 arithmetic encoder means; 
 
 modulation-transmission means; and 
 deocding means; 
 
       wherein said decoding means comprises a functional combination of a sequential decoder means which comprises a sequence of bistable elements, each of which can be set to represent encoded symbol bits, and an arithmetic decoder means; 
       specific bistable elements in said sequential decoder means being identified as fixed branch points; 
       wherein said arithmetic encoder means comprises input means for accepting a sequential plurality of allowed input symbols and output means for outputting an encoded sequence of bits for allowed symbols input thereinto, said arithmetic encoder means further having means for generating and, in a sequence expected by said arithmetic decoder means, outputting an encoded sequence of bits for at least one reserved symbol before and/or after an encoded allowed input symbol, which reserved symbol is not allowed as an input symbol to said arithmetic encoder means input means; 
       said arithmetic encoder means being functionally interconnected to said modulation-transmission means and said modulation-transmission means being functionally interconnected to said decoding means; 
       such that in use said arithmetic encoder means receives a sequence of allowed symbols at its input means and provides an encoded sequence of bits for at least some thereof in optional combination with at least one encoded reserved symbol in a pattern expected by said arithmetic decoder means, said sequence of bits being caused to arrive at said decoding means; 
       and said arithmetic decoder means having error detection means such that in use said arithmetic decoder means, upon detecting the absence of an expected encoded reserved symbol, or the presence of an unexpected encoded reserved symbol, initiates an error correction routine to the end that:
 selection is made of a series of sequential bits, said selection being made from a group consisting of a plurality of such series of sequential bits which result from the changing of bistable elements in said sequential decoder means at said specified branch points; 
 
       is performed;
 b. entering a sequence of symbols into said arithmetic encoder means such that said sequence of symbols are encoded and exited therefrom as a binary bit stream sequence; 
 c. monitoring output from said arithmetic decoder means for errors; 
 d. upon detection of an error by said arithmetic decoder means, producing a plurality of series of sequential bits which result from the changing of bistable elements in said sequential decoder means at said branch points by using fixed branch point bistable elements in said sequential decoder means; 
 e. determining which series of sequential bits in said produced plurality of series of sequential bits is most likely correct utilizing at least one selection from the group consisting of: 
 1. eliminating any series of sequential bits which contains an encoded reserved symbol; 
 2. applying a metric to at least two series of sequential bits which do not contain an encoded reserved symbol, to determine which of said at least two series of sequential bits is most likely correct; 
 3. applying an Euclidean metric to at least two series of sequential bits which do not contain an encoded reserved symbol, to determine which of said at least two series of sequential bits is most likely correct. 
 
     
     
       21. A system, comprising:
 a decoder, comprising an arithmetic decoder and a sequential decoder, configured to receive data from an arithmetic encoder via a channel,   wherein the arithmetic decoder, upon detecting an absence of an expected encoded reserved symbol or a presence of an unexpected encoded reserved symbol, is configured to initiate an error correction routine,   wherein the arithmetic decoder is configured to not initiate the error correction routine upon detection of an allowed symbol in the received data, and   wherein the sequential decoder is configured to, upon initiation of the error correction routine by the arithmetic decoder, change at least one bistable element in the sequential decoder or select a series of sequential bits from a plurality of series of sequential bits which result from the changing of bistable elements in the sequential decoder.   
     
     
       22. The system of claim 21, further comprising:
 the arithmetic encoder configured to receive input data; and   a modulator located between the arithmetic encoder and the channel.   
     
     
       23. The system of claim 21, wherein the decoder is configured for use in a communication system. 
     
     
       24. The system of claim 23, wherein the communication system is configured to use Binary Phase Shift Keying (BPSK), Quadrature Phase Shift Keying (QPSK), or Trellis Coded Modulation (TCM). 
     
     
       25. A method, comprising:
 receiving data from an encoder via a channel at a decoder, the decoder comprising an arithmetic decoder and a sequential decoder; and   producing output data using the decoder,   wherein the arithmetic decoder, upon detecting an absence of an expected encoded reserved symbol or a presence of an unexpected encoded reserved symbol, initiates an error correction routine,   wherein the arithmetic decoder does not initiate the error correction routine upon detection of an allowed symbol in the received data, and   wherein the sequential decoder, upon initiation of the error correction routine by the arithmetic decoder, changes at least one bistable element in the sequential decoder or selects a series of sequential bits from a plurality of series of sequential bits which result from the changing of bistable elements in the sequential decoder.   
     
     
       26. The method of claim 25, further comprising:
 receiving coded data from the encoder at a modulator, which outputs modulated data to the channel.   
     
     
       27. The method of claim 25, wherein the received data is a signal corresponding to a binary bit stream sequence of “1”/(“0”)'s and “0”/(“1”)'s. 
     
     
       28. The method of claim 27, wherein the producing output data further comprises making hard logic circuitry decisions as to a presence of the “1”/(“0”)'s and “0”/(“1”)'s based on the signal. 
     
     
       29. The method of claim 28, wherein the producing output data further comprises using the sequential decoder to monitor output from the arithmetic decoder for errors. 
     
     
       30. The method of claim 29, wherein the producing output data further comprises:
 identifying a branch point if the signal has a value located within a null zone; and   correcting the “1”/(“0”) or “0”/(“1”) binary bit by inverting it to “0”/(“1”) or “1”/(“0”) respectively, at the sequential decoder if an output from the arithmetic decoder indicates an error.   
     
     
       31. The method of claim 30, wherein the identifying a branch point and the correcting the “1”/(“0”) or “0”/(“1”) binary bit is performed more than once. 
     
     
       32. The method of claim 31, wherein the producing output data further comprises determining a number of branch points at which correction of the “1”/(“0”) or “0”/(“1”) binary bit has been performed (Kc). 
     
     
       33. The method of claim 32, wherein the producing output data further comprises:
 decreasing a value of Kc by 1 if a subsequent branch point is sequentially prior to a first branch point; and   increasing the value of Kc by 1 if the subsequent branch point is not sequentially prior to the first branch point.   
     
     
       34. The method of claim 32, further comprising:
 determining a Hamming distance threshold (Tc); and   expanding the null zone to increase a number of branch points, if the number of branch points at which correction has been performed (Kc) exceeds the Hamming distance threshold (Tc).   
     
     
       35. The method of claim 31, wherein the producing the output data further comprises:
 determining a Euclidean distance between the received data and the output data; and   expanding the null zone to increase a number of branch points, if the Euclidean distance for subsequent calculations increases faster than a defined rate.   
     
     
       36. The method of claim 25, wherein the producing the output data further comprises:
 selecting a series of sequential bits in the sequential decoder by,
 eliminating any series of sequential bits which contains an encoded reserved symbol; 
 applying a metric to at least two series of sequential bits which do not contain an encoded reserved symbol and determining which series is most likely correct; or 
 applying an Euclidean metric to at least two series of sequential bits which do not contain an encoded reserved symbol and determining which series is most likely correct. 
   
     
     
       37. The method of claim 25, further comprising using the decoder in a communication system. 
     
     
       38. The method of claim 37, further comprising using Binary Phase Shift Keying (BPSK), Quadrature Phase Shift Keying (QPSK), or Trellis Coded Modulation (TCM) in the communication system. 
     
     
       39. A system, comprising:
 a decoder, comprising an encoded symbol decoder and a sequential decoder, configured to receive data from an arithmetic encoder via a channel,   wherein the encoded symbol decoder, upon detecting an absence of an expected encoded reserved symbol or a presence of an unexpected encoded reserved symbol, is configured to initiate an error correction routine,   wherein the encoded symbol decoder is configured to not initiate the error correction routine upon detection of an allowed symbol in the received data, and   wherein the sequential decoder is configured to, upon initiation of the error correction routine by the encoded symbol decoder, change at least one bistable element in the sequential decoder or select a series of sequential bits from a plurality of series of sequential bits which result from the changing of bistable elements in the sequential decoder.   
     
     
       40. The system of claim 39, wherein the encoded symbol decoder is an arithmetic decoder. 
     
     
       41. The system of claim 39, further comprising:
 the arithmetic encoder configured to receive input data; and   a modulator located between the encoder and the channel.   
     
     
       42. The system of claim 39, wherein the decoder is configured for use in a communication system. 
     
     
       43. The system of claim 39, wherein the communication system is configured to use Binary Phase Shift Keying (BPSK), Quadrature Phase Shift Keying (QPSK), or Trellis Coded Modulation (TCM). 
     
     
       44. A method, comprising:
 receiving data from an encoder via a channel at a decoder, comprising an encoded symbol decoder and a sequential decoder; and   producing output data using the decoder,   wherein the encoded symbol decoder, upon detecting an absence of an expected encoded reserved symbol or a presence of an unexpected encoded reserved symbol, initiates an error correction routine,   wherein the encoded symbol decoder does not initiate the error correction routine upon detection of an allowed symbol in the received data, and   wherein the sequential decoder, upon initiation of the error correction routine by the encoded symbol decoder, changes at least one bistable element in the sequential decoder or selects a series of sequential bits from a plurality of series of sequential bits which result from the changing of bistable elements in the sequential decoder.   
     
     
       45. The method of claim 44, further comprising:
 receiving the data from the encoder via a modulator, which outputs data to the channel.   
     
     
       46. The method of claim 44, further comprising using an arithmetic encoder as the encoder and an arithmetic decoder as the encoded symbol decoder. 
     
     
       47. The method of claim 44, further comprising using a signal corresponding to a binary bit stream sequence of “1”/(“0”)'s and “0”/(“1”)'s as the received data. 
     
     
       48. The method of claim 47, wherein the producing output data further comprises making hard logic circuitry decisions as to a presence of the “1”/(“0”)'s and “0”/(“1”)'s based on the signal. 
     
     
       49. The method of claim 48, wherein the producing output data further comprises using the sequential decoder to monitor output from the encoded symbol decoder for errors. 
     
     
       50. The method of claim 49, wherein the producing output data further comprises:
 identifying a branch point if the signal has a value located within a null zone; and   correcting the “1”/(“0”) or “0”/(“1”) binary bit by inverting it to “0”/(“1”) or “1”/(“0”) respectively, in the sequential decoder if an output from the encoded symbol decoder indicates an error.   
     
     
       51. The method of claim 50, wherein the identifying a branch point and the correcting the “1”/(“0”) or “0”/(“1”) binary bit is performed more than once. 
     
     
       52. The method of claim 51, wherein the producing output data further comprises determining a number of branch points at which correction of the “1”/(“0”) or “0”/(“1”) binary bit has been performed (Kc). 
     
     
       53. The method of claim 52, wherein the producing output data further comprises:
 decreasing a value of Kc by 1 if a subsequent branch point is sequentially prior to a first branch point; and   increasing the value of Kc by 1 if the subsequent branch point is not sequentially prior to the first branch point.   
     
     
       54. The method of claim 52, further comprising:
 determining a Hamming distance threshold (Tc); and   expanding the null zone to increase a number of branch points, if the number of branch points at which correction has been performed (Kc) exceeds the Hamming distance threshold (Tc).   
     
     
       55. The method of claim 51, wherein the producing output data further comprises:
 determining a Euclidean distance between the received data and the output data; and   expanding the null zone to increase a number of branch points, if the Euclidean distance for subsequent calculations increases faster than a defined rate.   
     
     
       56. The method of claim 51, wherein the producing the output data further comprises:
 selecting a series of sequential bits in the sequential decoder by,
 eliminating any series of sequential bits which contains an encoded reserved symbol; 
 applying a metric to at least two series of sequential bits which do not contain an encoded reserved symbol and determining which series is most likely correct; or 
 applying an Euclidean metric to at least two series of sequential bits which do not contain an encoded reserved symbol and determining which series is most likely correct. 
   
     
     
       57. The method of claim 44, further comprising using the decoder in a communication system. 
     
     
       58. The method of claim 57, further comprising using Binary Phase Shift Keying (BPSK), Quadrature Phase Shift Keying (QPSK), or Trellis Coded Modulation (TCM) in the communication system.