DLL circuit and camcorder using DLL circuit

Abstract

A DLL circuit which can prevent transition to a pseudo lock state is provided. The DLL circuit includes a delay stage to which a reference clock is input and in which variable delay elements D able to change an amount of delay are connected in a plurality of stages, a phase comparator (PH Comp) which compares the phase of the reference clock to the phase of one delay signal extracted from the delay stage, a delay control circuit which performs delay control of the delay element in the delay stage on the basis of the comparison result by the phase-comparison means, and a DFF which detects a phase relationship of at least two delay signals extracted from the delay stage to discriminate a state which is not a normal lock state and controls the delay control circuit to perform state transition to the normal lock state.

What is claimed is: 
     
       1. A DLL circuit comprising:
 a delay stage to which a reference clock is input and in which delay elements able to change an amount of delay are connected in a plurality of stages; 
 phase-comparison means for comparing a phase of the reference clock to the phase of one of delay signals extracted from said delay stage; 
 controlling means for controlling the amount of delay of said delay stage on the basis of the comparison result by said phase-comparison means; 
 state transition means for detecting a phase relationship of at least two delay signals extracted from said delay stage to discriminate a state which is not a normal lock state and for controlling said controlling means to transit the state to the normal lock state; and 
 means for controlling said controlling means so as to minimize the amount of delay in starting up the DLL circuit. 
 
     
     
       2. A DLL circuit according to  claim 1 , wherein reversal of a delay relationship of the phase of one of the delay signals to the phase of another delay signal is detected in detection of a phase relationship of said state transition means. 
     
     
       3. A DLL circuit according to  claim 1 , wherein said state transition means is an edge trigger type of data input flip-flop circuit, a delay signal of a previous stage having a smaller amount of delay extracted from said delay stage is connected to a clock input of said flip-flop circuit, and the delay signal of a subsequent stage having a larger amount of delay is connected to a data input of said flip-flop circuit. 
     
     
       4. A camcorder having a DLL circuit according to  claim 1 . 
     
     
       5. A DLL circuit comprising:
 a delay stage to which a reference clock is input and in which delay elements able to change an amount of delay are connected in a plurality of stages; 
 phase-comparison means for comparing a phase of the reference clock to the phase of one of delay signals extracted from said delay stage; 
 controlling means for controlling the amount of delay of said delay stage on the basis of the comparison result by said phase-comparison means; and 
 state transition means for controlling said controlling means so that the amount of delay of said delay stage is minimized in starting up the DLL circuit, for detecting a phase relationship of at least two delay signals extracted from said delay stage to discriminate a state which is not a normal lock state except the start-up of the DLL circuit and for controlling said controlling means to transit the state to the normal lock state. 
 
     
     
       6. A DLL circuit comprising:
 a delay stage to which a reference clock is input and in which delay elements able to change an amount of delay are connected in a plurality of stages; 
 phase-comparison means for comparing a phase of the reference clock to the phase of one of delay signals extracted from said delay stage; 
 controlling means for controlling the amount of delay of said delay stage on the basis of the comparison result by said phase-comparison means; and 
 a plurality of state transition means for detecting a phase relationship of at least two delay signals extracted from said delay stage to discriminate a state which is not a normal lock state and for controlling said controlling means to transit the state to the normal lock state. 
 
     
     
       7. A DLL circuit comprising:
 a delay stage inputting a reference clock, and comprising a plurality of delay elements connected in a plurality of stages which output delay clocks, wherein delay times of the delay elements are controllable;   a phase comparator for checking an intermediate delay in said delay stage;   control means for controlling the delay times of the delay elements on the basis of the intermediate delay checked by said phase comparator to be locked with the reference clock; and   state transition means for detecting a phase relationship of delay clocks from said delay stage to determine if a state of the DLL circuit is a normal lock state, wherein   said control means is reset in either case of when said state transition means determines that the DLL circuit is not in the normal lock state or when starting up the DLL circuit, and   the delay time of said delay stage is minimized through the resetting of said control means.   
     
     
       8. A camera comprising a DLL circuit according to claim 7.