Preventing drain to body forward bias in a MOS transistor

Abstract

A voltage level shifting circuit (FIG. 4 ) has a plurality of PMOS transistors M 1 , M 2 , M 3 connected in parallel for respectively driving a capacitive load C L with a selected different voltage level V 1 , V 2 or V 3 . Transistors M 1 , M 2 , M 3 are controlled so that one of them is placed in the ON condition, with the others in the OFF condition, to connect one of the voltages V 1 , V 2 or V 3 to charge the load CL. The largest voltage transistor M 3 has its body connected to its source. The lower voltage transistors M 1 , M 2 have their bodies respectively connected to switches S 1 , S 2 , which connect the bodies to the sources when the transistors are placed in the ON condition and connect the bodies to the highest voltage V 3 when the transistors are placed in the OFF condition.

1. A method for preventing a source-to-body forward bias condition of a PN junction between a drain and a body in a MOS transistor, the method comprising:
 applying voltage to the a gate of the MOS transistor to place the MOS transistor in an ON condition enabling flow of current between the a source and the drain of the MOS transistor, the source being at a source voltage; 
 connecting the body of the MOS transistor to the transistor source for the ON condition; 
 applying voltage to the gate of the MOS transistor to place the MOS transistor in an OFF condition preventing flow of current between the source and the drain of the MOS transistor; and 
 switching the body of the MOS transistor from the source to a voltage different than the transistor source voltage for the OFF condition; the different voltage acting to place the PN junction between the drain and the body of the MOS transistor in a source-to-body reverse bias condition, when keeping the transistor body connected to the transistor source would place the PN junction between the drain and the body of the MOS transistor in a source-to-body forward bias condition, wherein the voltage applied to the gate to place the MOS transistor in the OFF condition is the same as the different voltage. 
 
     
     
       2. The method of  claim 1 , wherein the voltage applied to the transistor gate to place the transistor in the OFF condition is the same as the different voltage. 
     
     
       3. The method of  claim 1 , wherein the MOS transistor is a PMOS transistor with its source connected to a first reference voltage and its drain connected to ground through a load; and wherein in the OFF condition the transistor drain is switched to a second reference voltage greater than the first reference voltage. 
     
     
       4. The method of  claim 3 , wherein the different voltage is the same as the second reference voltage. 
     
     
       5. The method of  claim 4 , wherein the voltage applied to the transistor gate to place the MOS transistor in the OFF condition is the same as the second reference voltage. 
     
     
       6. A method for preventing a forward source-to-body bias condition in a PN junction between a drain and a body of a MOS transistor in a circuit having a plurality of MOS transistors connected in parallel and respectively to a corresponding plurality of reference voltages, the method comprising:
 applying voltage to the a gate of a first one of the plurality of MOS transistors to place the first MOS transistor in an ON condition enabling flow of current between the a source and a drain of the first MOS transistor to apply a first one of the plurality of reference voltages to a load, the source of the first MOS transistor being at the first one of the plurality of reference voltages; 
 connecting the a body of the first MOS transistor to the first transistor source for the ON condition; 
 applying voltage to the gate of the first MOS transistor to place the first MOS transistor in an OFF condition preventing flow of current between the source and the drain of the first MOS transistor; 
 applying voltage to the a gate of a second one of the plurality of MOS transistors to place the second MOS transistor in an ON condition enabling flow of current between the a source and a drain of the second MOS transistor to apply a second one of the plurality of reference voltages to the load and to the drain of the first MOS transistor; and 
 switching the body of the first MOS transistor from the first transistor source to a voltage different than the first one of the plurality of reference voltage voltages for the second MOS transistor ON condition; the different voltage acting to place a PN junction between the drain and the body of the first MOS transistor in the a reverse bias condition, when keeping the first MOS transistor body connected to the first MOS transistor source would place the PN junction between the drain and the body of the first MOS transistor in a source-to-body forward bias condition. 
 
     
     
       7. A voltage level shifting circuit, comprising:
 a plurality of MOS transistors connected in parallel to act as main switches for selective connection of respective different reference voltage sources to a capacitive load; 
 auxiliary switches provided to connect the a body of each main switch, either to its source when that main switch is in the an ON condition or to the a highest one of the reference voltage sources when that main switch is in the an OFF condition.