Write-assisted SRAM bit cell

Abstract

An SRAM bit cell with cross-coupled inverters has separate write and read buses. Writing is performed through an NMOS pass transistor. Reading is performed through a PMOS transistor. Because the NMOS transistor does not pass a logic 1 as easily as logic 0, assistance is needed to speed up writing of a logic 1 value relative to the time required to write a logic 0 value. An NMOS pre-charge transistor is coupled between the read bus and ground potential; and, a read is performed simultaneously with a write. This conditions the cell by weakening one of the inverters, such that they cross-couple more quickly when a logic 1 value is written into the cell. Alternatively, a single-ended read/write bus can be coupled to the NMOS pass transistor with write-assistance provided by grounding the PMOS pass transistor.

1. A memory bit cell comprising cross-coupled first and second inverters, each one of the inverters further comprising a pull-up transistor and a pull-down transistor having series-connected terminals defining a storage node, a first pass transistor coupled between a write bus and a first one of the storage nodes, a second pass transistor coupled between a read bus and a second one of the storage nodes, the first pass transistor further coupled to a write enable line for controllably switching the first pass transistor on or off, the second pass transistor further coupled to a read enable line for controllably switching the second pass transistor on or off, and a pre-charge transistor coupled between the read bus and a logic low voltage reference signal source, wherein one of the first and second pass transistors is an NMOS transistor and the other one of the first and second pass transistors is a PMOS transistor. 
     
     
       2. A bit cell as defined in  claim 1 , wherein:
 (a) the pull-down transistors, the first pass transistor and the pre-charge transistor are NMOS transistors; and,  
 (b) the pull-up transistors and the second pass transistor are PMOS transistors.  
 
     
     
       3. A bit cell as defined in  claim 2 , wherein the series-connected terminals further comprise drain terminals of the respective inverter pull-down transistors, a logic high voltage reference signal is applied to a source terminal of each one of the pull-up transistors, the logic low voltage reference signal is applied to a source terminal of each one of the pull-down transistors, a switching terminal of the first inverter pull-up transistor is coupled to a switching terminal of the first inverter pull-down transistor, a switching terminal of the second inverter pull-up transistor is coupled to a switching terminal of the second inverter pull-down transistor, the first inverter pull-up and pull-down transistor switching terminals are further coupled to the second inverter series-connected terminals, the second inverter pull-up and pull-down transistor switching terminals are further coupled to the first inverter series-connected terminals, a source-to-drain path of the first pass transistor is coupled between the write bus and the first storage node, a source-to-drain path of the second pass transistor is coupled between the read bus and the second storage node, a source-to-drain path of the pre-charge transistor is coupled between the read bus and the logic low voltage reference signal source, a switching terminal of the first pass transistor is coupled to the write enable line, a switching terminal of the second pass transistor is coupled to the read enable line, and a switching terminal of the pre-charge transistor is coupled to a pre-charge enable line. 
     
     
       4. A bit cell as defined in  claim 3 , further comprising circuitry for:
 (a) logically combining decoded X and Y read signals to produce a read enable signal;  
 (b) logically inverting the read enable signal to produce a complementary read enable signal;  
 (c) applying the complementary read enable signal to the read enable line to turn the second pass transistor on;  
 (d) logically combining a write strobe signal when the read enable signal to produce a write enable signal;  
 (e) applying the write enable signal to the write enable line to turn the first pass transistor on;  
 (f) if the pre-charge transistor is off, applying a pre-charge enable signal to the pre-charge enable line to turn the pre-charge transistor on; and,  
 (g) if the pre-charge transistor is on, applying the pre-charge enable signal to the pre-charge enable line to keep the pre-charge transistor turned on;  
 while simultaneously: 
 (i) writing data on the write bus into the bit cell;  
 (ii) reading data from the bit cell onto the read bus; and,  
 (iii) maintaining the read bus in a logic low state.  
 
 
     
     
       5. A bit cell as defined in  claim 4 , the driver for further:
 (a) applying a logical complement of the write enable signal to the write enable line to turn the first pass transistor off;  
 (b) applying the complementary read enable signal to the read enable line to turn the second pass transistor on; and,  
 (c) initially applying the pre-charge enable signal to the pre-charge enable line to initially turn the pre-charge transistor on, then applying a logical complement of the pre-charge enable signal to the pre-charge enable line to turn the pre-charge transistor off for a brief time interval, then applying the pre-charge enable signal to the pre-charge enable line to turn the pre-charge transistor on;  
 while reading data from the bit cell onto the read bus without simultaneously writing data on the write bus into the bit cell.  
 
     
     
       6. A multiple-row and multiple-column memory array comprising a plurality of bit cells, each one of the bit cells further comprising first and second inverters cross-coupled to define first and second storage nodes, a first pass transistor coupled between a write bus and the first storage node, a second pass transistor coupled between a read bus and the second storage node, the first pass transistor further coupled to a write enable line for controllably switching the first pass transistor on or off, the second pass transistor further coupled to a read enable line for controllably switching the second pass transistor on or off, one of the first and second pass transistors being an NMOS transistor and the other one of the first and second pass transistors being a PMOS transistor, wherein each write bus is grouped into one of:
 (i)  a plurality of high memory parts;  and,   
 (ii)  a plurality of low memory parts;  
 the memory array further comprising, for each read bus, a pre-charge transistor coupled between the read bus and a logic low voltage reference signal source.  
 
     
     
       7. A memory array as defined in  claim 6 , wherein:
 (a) the first inverter further comprises a first pull-up transistor and a first pull-down transistor having series-connected terminals defining the first storage node;  
 (b) the second inverter further comprises a second pull-up transistor and a second pull-down transistor having series-connected terminals defining the second storage node;  
 (c) the pull-down transistors, the first pass transistors and the pre-charge transistor are NMOS transistors; and,  
 (d) the pull-up transistors and the second pass transistors are PMOS transistors.  
 
     
     
       8. A memory array as defined in  claim 7 , wherein the series-connected terminals further comprise drain terminals of the respective inverter pull-up and pull-down transistors, the logic high voltage reference signal is applied to a source terminal of each one of the pull-up transistors, the logic low voltage reference signal is applied to a source terminal of each one of the pull-down transistors, a switching terminal of the first inverter pull-up transistor is coupled to a switching terminal of the first inverter pull-up transistor, a switching terminal of the second inverter pull-up transistor is coupled to a switching terminal of the second inverter pull-down transistor, the first inverter pull-up and pull-down transistor switching terminals are further coupled to the second inverter series-connected terminals, the second inverter pull-up and pull-down transistor switching terminals are further coupled to the first inverter series-connected terminals, a source-to-drain path of the first pass transistor is coupled between the write bus and the first voltage node, a source-to-drain path of the second transistor is coupled between the read bus and the second storage node, a source-to-drain path of the pre-charge transistor is coupled between the read bus and the logic low voltage reference signal source, a switching terminal of the first pass transistor is coupled to the write enable line, a switching terminal of the second pass transistor is coupled to the read enable line, a switching terminal of the pre-charge transistor is coupled to a pre-charge enable line. 
     
     
       9. A memory array as defined in  claim 8 , the driver for further:
 (a) applying a logical complement of the write enable signal to the write enable line to turn off the first pass transistor in each bit cell in the row;  
 (b) applying the complementary read enable signal to the read enable line to turn on the second pass transistor in each bit cell in the row;  
 (c) for each pre-charge transistor coupled to the row: 
 (i) initially applying the pre-charge enable signal to the pre-charge transistor to initially turn the pre-charge transistor on;  
 (ii) then applying a logical complement of the pre-charge enable signal to the pre-charge transistor for a brief time interval to turn the pre-charge transistor off for the brief time interval; and,  
 (iii) then applying the pre-charge enable signal to the pre-charge transistor to turn the pre-charge transistor on;  
 
 while reading data from each bit cell in the row onto the read bus without simultaneously writing data on the write bus into each bit cell in the row.  
 
     
     
       10. A memory array as defined in  claim 6 , further comprising, for each row, a driver for:
 (a) logically combining decoded X and Y read signals to produce a read enable signal;  
 (b) logically inverting the read enable signal to produce a complementary read enable signal;  
 (c) applying the complementary read enable signal to the read enable line to turn on the second pass transistor in each bit cell in the row;  
 (d) logically combining a write strobe signal when the read enable signal to produce a write enable signal;  
 (e) applying the write enable signal to the write enable line to turn on the first pass transistor in each bit cell in the row;  
 (f) for each pre-charge transistor coupled to the row: 
 (i) if the pre-charge transistor is off, applying a pre-charge enable signal to the pre-charge transistor to turn the pre-charge transistor on; and,  
 (ii) if the pre-charge transistor is on, applying the pre-charge enable signal to the pre-charge transistor to keep the pre-charge transistor turned on;  
 
 while simultaneously writing data on the write bus into each bit cell in the row and reading data from each bit cell in the row onto the read bus.  
 
     
     
       11. A method of writing a binary digital value asserted on a write bus into a memory bit cell, the bit cell comprising first and second inverters cross-coupled to define first and second storage nodes, a first pass transistor coupled between the write bus and the first storage node, a second pass transistor coupled between a read bus and the second storage node, the first pass transistor further coupled to a write enable line for controllably switching the first pass transistor on or off, the second pass transistor further coupled to a read enable line for controllably switching the second pass transistor on or off, and a pre-charge transistor coupled between the read bus and a logic low voltage reference signal source, the method comprising:
 (a) turning the first pass transistor on;  
 (b) turning the second pass transistor on;  
 (c) if the pre-charge transistor is off, turning the pre-charge transistor on; and,  
 (d) if the pre-charge transistor is on, keeping the pre-charge transistor turned on.  
 
     
     
       12. A method of reading onto a read bus a binary digit value stored in a memory bit cell, the bit cell comprising first and second inverters cross-coupled to define first and second storage nodes, a first pass transistor coupled between the write bus and the first storage node, a second pass transistor coupled between a read bus and the second storage node, the first pass transistor further coupled to a write enable line for controllably switching the first pass transistor on or off, the second pass transistor further coupled to a read enable line for controllably switching the second pass transistor on or off, a pre-charge transistor coupled between the read bus and a logic low voltage reference signal source, the method comprising:
 (a) turning the first pass transistor off;  
 (b) turning the second pass transistor on; and,  
 (c) initially turning the pre-charge transistor on, then turning the pre-charge transistor off for a brief time interval, then turning the pre-charge transistor on.  
 
     
     
       13. A memory bit cell comprising first and second inverters cross-coupled to define first and second storage nodes, a first pass transistor coupled between a read/write bus and the first storage node, a second pass transistor coupled between a logic low voltage reference signal source and the second storage node, the first pass transistor further coupled to a read/write enable line for controllably switching the first pass transistor on or off, the second pass transistor further coupled to a write assist line for controllably switching the second pass transistor on or off, wherein one of the first and second pass transistors is an NMOS transistor and the other one of the first and second pass transistors is a PMOS transistor. 
     
     
       14. A bit cell as defined in  claim 13 , wherein:
 (a) the first inverter further comprises a first pull-up transistor and a first pull-down transistor having series-connected terminals defining the first storage node;  
 (b) the second inverter further comprises a second pull-up transistor and a second pull-down transistor having series-connected terminals defining the second storage node;  
 (c) the pull-down transistors and the first pass transistor are NMOS transistors; and,  
 (d) the pull-up transistors and the second pass transistor are PMOS transistors.  
 
     
     
       15. A bit cell as defined in  claim 14 , wherein the series-connected terminals further comprise drain terminals of the respective inverter pull-up and pull-down transistors, a logic high voltage reference signal is applied to a source terminal of each one of the pull-up transistors, the logic low voltage reference signal is applied to a source terminal of each one of the pull-down transistors, a switching terminal of the first inverter pull-up transistor is coupled to a switching terminal of the first inverter pull-down transistor, a switching terminal of the second inverter pull-up transistor is coupled to a switching terminal of the second inverter pull-down transistor, the first inverter pull-up and pull-down transistor switching terminals are further coupled to the second inverter series-connected terminals, the second inverter pull-up and pull-down transistor switching terminals are further coupled to the first inverter series-connected terminals, a source-to-drain path of the first pass transistor is coupled between the read/write bus and the first storage node, a source-to-drain path of the second pass transistor is coupled between the logic low voltage reference signal source and the second storage node, a switching terminal of the first pass transistor is coupled to the read/write enable line, and a switching terminal of the second pass transistor is coupled to the write assist line. 
     
     
       16. A bit cell as defined in  claim 15 , further comprising circuitry for:
 (a) logically combining decoded X and Y read signals to produce a read/write enable signal;  
 (b) applying the read/write enable signal to the read/write enable line to turn the first pass transistor on;  
 (c) logically combining a write strobe signal with the read/write enable signal to produce a write assist signal; and,  
 (d) applying the write assist signal to the write assist line to turn the second pass transistor on;  
 while either: 
 (i) writing data on the read/write bus into the bit cell; or,  
 (ii) reading data from the bit cell onto the read/write bus.  
 
 
     
     
       17. A multiple-row and multiple-column memory array comprising a plurality of bit cells, each bit cell comprising first and second inverters cross-coupled to define first and second storage nodes, a first pass transistor coupled between a read/write bus and the first storage node, a second pass transistor coupled between a logic low voltage reference signal source and the second storage node, the first pass transistor further coupled to a read/write enable line for controllably switching the first pass transistor on or off, the second pass transistor further coupled to a write assist line for controllably switching the second pass transistor on or off, one of the first and second pass transistors being an NMOS transistor and the other one of the first and second pass transistors being a PMOS transistor, wherein each read/write enable line is grouped into one of:
 (i) a plurality of high memory parts; and,  
 (ii) a plurality of low memory parts.  
 
     
     
       18. A memory array as defined in  claim 17 , wherein:
 (a) the first inverter further comprises a first pull-up transistor and a first pull-down transistor having series-connected terminals defining the first storage node;  
 (b) the second inverter further comprises a second pull-up transistor and a second pull-down transistor having series-connected terminals defining the second storage node;  
 (c) the pull-down transistors and the first pass transistors are NMOS transistors; and,  
 (d) the pull-up transistors and the second pass transistors are PMOS transistors.  
 
     
     
       19. A memory array as defined in  claim 18 , wherein the series-connected terminals further comprise drain terminals of the respective inverter pull-up and pull-down transistors, the logic high voltage reference signal is applied to a source terminal of each one of the pull-up transistors, the logic low voltage reference signal is applied to a source terminal of each one of the pull-down transistors, a switching terminal of the first inverter pull-up transistor is coupled to a switching terminal of the first inverter pull-down transistor, a switching terminal of the second inverter pull-up transistor is coupled to a switching terminal of the second inverter pull-down transistor, the first inverter pull-up and pull-down transistor switching terminals are further coupled to the second inverter series-connected terminals, the second inverter pull-up and pull-down transistor switching terminals are further coupled to the first inverter series-connected terminals, a source-to-drain path of the first pass transistor is coupled between the read/write bus and the first storage node, a source-to-drain path of the second transistor is coupled between the logic low voltage reference signal source and the second storage node, a switching terminal of the first pass transistor coupled to the read/write enable line, and a switching terminal of the second pass transistor is coupled to the write assist line. 
     
     
       20. A memory array as defined in  claim 17 , further comprising, for each row, a driver for:
 (a) logically combining decoded X and Y read signals to produce a read/write enable signal;  
 (b) applying the read/write enable signal to the read/write enable line to turn on the first pass transistor in each bit cell in the row;  
 (c) logically combining a write strobe signal with the read/write enable signal to produce a write assist signal; and,  
 (d) applying the write assist signal to the write assist line to turn the second pass transistor in each bit cell in the row;  
 while either: 
 (i) writing data on the read/write bus into the bit cell; or,  
 (ii) reading data from the bit cell onto the read/write bus.  
 
 
     
     
       21. A method of writing a binary digital value asserted on a read/write bus into a memory bit cell, the bit cell comprising first and second inverters cross-coupled to define first and second storage nodes, a first pass transistor coupled between the read/write bus and the first storage node, a second pass transistor coupled between a logic low voltage reference signal source and the second storage node, the first pass transistor further coupled to a read/write enable line for controllably switching the first pass transistor on or off, the second pass transistor further coupled to a write assisted line for controllably switching the second pass transistor on or off, the method comprising turning the first and second pass transistors on. 
     
     
       22. A method of reading onto a read/write bus a binary digit value stored in a memory bit cell, the bit cell comprising first and second inverters cross-coupled to define first and second storage nodes, a first pass transistor coupled between the read/write bus and the first storage node, a second pass transistor coupled between a logic low voltage reference signal source and the second storage node, the first pass transistor further coupled to a read/write enable line for controllably switching the first pass transistor on or off, the second pass transistor further coupled to a write assist line for controllably switching the second pass transistor on or off, the method comprising turing the first pass transistor on and turning the second pass transistor off. 
     
     
       23. A memory array comprising a plurality of pairs of bit cells, each pair of bit cells further comprising:
 (a) first and second inverters cross-coupled to define first and second storage nodes, a first pass transistor coupled between a read/write bus and the first storage node, a second pass transistor coupled between a logic low voltage reference signal source and the second storage node, the first pass transistor further coupled to a first read/write enable line for controllably switching the first pass transistor on or off, the second pass transistor further coupled to a write assist line for controllably switching the second pass transistor on or off, one of the first and second pass transistors being an NMOS transistor and the other one of the first and second pass transistors being a PMOS transistor; and,  
 (b) third and fourth inverters cross-coupled to define third and fourth storage nodes, a third pass transistor coupled between the read/write bus and the third storage node, a fourth pass transistor coupled between the logic low voltage reference signal source and the fourth storage node, the third pass transistor further coupled to a second read/write enable line for controllably switching the third pass transistor on or off, the fourth pass transistor further coupled to the write assist line for controllably switching the fourth pass transistor on or off, one of the third and fourth pass transistors being an NMOS transistor and the other one of the third and fourth pass transistors being a PMOS transistor.  
 
     
     
       24. A memory array as defined in  claim 23 , wherein the first and third pass transistors are NMOS transistors and the second and fourth pass transistors are PMOS transistors. 
     
     
       25. A memory array comprising a plurality of pairs of bit cells, each pair of bit cells further comprising:
 (a) first and second inverters cross-coupled to define first and second storage nodes, a first pass transistor coupled between a first read/write bus and the first storage node, a second pass transistor coupled between a logic low voltage reference signal source and the second storage node, the first pass transistor further coupled to a read/write enable line for controllably switching the first pass transistor on or off, the second pass transistor further coupled to a write assist line for controllably switching the second pass transistor on or off, one of the first and second pass transistors being an NMOS transistor and the other one of the first and second pass transistors being a PMOS transistor; and,  
 (b) third and fourth inverters cross-coupled to define third and fourth storage nodes, a third pass transistor coupled between a second read/write bus and the third storage node, a fourth pass transistor coupled between the logic low voltage reference signal source and the fourth storage node, the third pass transistor further coupled to the read/write enable line for controllably switching the third pass transistor on or off, the fourth pass transistor further coupled to the write assist line for controllably switching the fourth pass transistor on or off, one of the third and fourth pass transistors being an NMOS transistor and the other one of the third and fourth pass transistors being a PMOS transistor.  
 
     
     
       26. A memory array as defined in  claim 25 , wherein the first and third pass transistors are NMOS transistors and the second and fourth pass transistors are PMOS transistors. 
     
     
       27. A memory array comprising a plurality of quadruplets of bit cells, each quadruplet of bit cells further comprising:
 (a) first and second inverters cross-coupled to define first and second storage nodes, a first pass transistor coupled between a first read/write bus and the first storage node, a second pass transistor coupled between a logic low voltage reference signal source and the second storage node, the first pass transistor further coupled to a first read/write enable line for controllably switching the first pass transistor on or off, the second pass transistor further coupled to a write assist line for controllably switching the second pass transistor on or off, one of the first and second pass transistors being an NMOS transistor and the other one of the first and second pass transistors being a PMOS transistor;  
 (b) third and fourth inverters cross-coupled to define third and fourth storage nodes, a third pass transistor coupled between the first read/write bus and the third storage node, a fourth pass transistor coupled between the logic low voltage reference signal source and the fourth storage node, the third pass transistor further coupled to a second read/write enable line for controllably switching the third pass transistor on or off, the fourth pass transistor further coupled to the write assist line for controllably switching the fourth pass transistor on or off, one of the third and fourth pass transistors being an NMOS transistor and the other one of the third and fourth pass transistors being a PMOS transistor;  
 (c) fifth and sixth inverters cross-coupled to define fifth and sixth storage nodes, a fifth pass transistor coupled between a second read/write bus and a fifth storage node, a sixth pass transistor coupled between the logic low voltage reference signal source and the sixth storage node, the fifth pass transistor further coupled to the first read/write enable time for controllably switching the fifth pass transistor on or off, the sixth pass transistor further coupled to the write assist line for controllably switching the sixth pass transistor on or off, one of the fifth and sixth pass transistors being an NMOS transistor and the other one of the fifth and sixth pass transistors being a PMOS transistor; and,  
 (d) seventh and eighth inverters cross-coupled to define seventh and eighth storage nodes, a seventh pass transistor coupled between the second read/write bus and the seventh storage node, an eighth pass transistor coupled between the logic low voltage reference signal source and the eighth storage node, the seventh pass transistor further coupled to the second read/write enable line for controllably switching the seventh pass transistor on or off, the eighth pass transistor further coupled to the write assist line for controllably switching the eighth pass transistor on or off, one of the seventh and eighth pass transistors being an NMOS transistor and the other one of the seventh and eighth pass transistors being a PMOS transistor.  
 
     
     
       28. A memory array as defined in  claim 27 , wherein the first, third, fifth and seventh pass transistors are NMOS transistors and the second, fourth, sixth and eighth pass transistors are PMOS transistors. 
     
     
       29. A memory cell, comprising:
   a pair of inverters, wherein the pair of inventors comprise a first storage node and a second storage node;        a first pass transistor coupled between the first storage node and a write bus;        a write enable line coupled to a switching terminal of the first pass transistor;        a second pass transistor coupled between the second storage node and a read bus;        a read enable line coupled to a switching terminal of the second pass transistor;        a precharge transistor coupled to the read bus; and        a precharge enable signal coupled to a switching terminal of the precharge transistor.      
     
     
       30. The memory cell of  claim 29 , wherein:
   a first inverter of the pair of inverters comprises a PMOS pull - up transistor and an NMOS pull - down transistor, and further wherein the pull - up transistor and the pull - down transistor of the first inverter define the first storage node;        a second inverter of the pair of inverters comprises a PMOS pull - up transistor and an NMOS pull - down transistor, and further wherein the pull - up transistor and the pull - down transistor of the second inverter define the second storage node; and        the first pass transistor comprises an NMOS transistor, the second pass transistor comprises a PMOS transistor, and the precharge transistor comprises an NMOS transistor.      
     
     
       31. The memory cell of  claim 30 , wherein each one of the inverters further comprises series- connected terminals defining one of the storage nodes, the series - connected terminals further comprising:      drain terminals of the respective inverter pull - up and pull - down transistors coupled together,        a logically high voltage reference signal applied to a source terminal of each one of the pull - up transistors,        a logically low voltage reference signal applied to a source terminal of each one of the pull-down transistors,        a switching terminal of the first inverter pull - up transistor coupled to a switching terminal of the first inverter pull - down transistor,        a switching terminal of the second inverter pull - up transistor coupled to a switching terminal of the second inverter pull - down transistor,        the first inverter pull - up and pull - down transistor switching terminals further coupled to the second inverter series - connected terminals,        the second inverter pull - up and pull - down transistor switching terminals further coupled to the first inverter series - connected terminals,        a source - to - drain path of the first pass transistor coupled between the write bus and the first storage node,        a source - to - drain path of the second pass transistor coupled between the read bus and the second storage node, and        a source - to - drain path of the pre - charge transistor coupled between the read bus and the logic low voltage reference signal source.      
     
     
       32. The memory cell of  claim 31 , further comprising drive circuitry capable of:
   logically combining decoded first and second read signals to produce a read enable signal;        logically inverting the read enable signal to produce a complementary read enable signal;        applying the complementary read enable signal to the read enable line to turn the second pass transistor on;        logically combining a write strobe signal with the read enable signal to produce a write enable signal;        applying the write enable signal to the write enable line to turn the first pass transistor on;        if the pre - charge transistor is off, applying a pre - charge enable signal to the pre - charge enable line to turn the precharge transistor on; and,        if the pre - charge transistor is on, applying the pre - charge enable signal to the pre - charge enable line to keep the precharge transistor turned on;        while concurrently:      writing data on the write bus into the bit cell;        reading data from the bit cell onto the read bus; and,        maintaining the read bus in a logically low state.        
     
     
       33. The memory cell of  claim 32 , wherein the drive circuitry is further capable of:
   applying a logical complement of the write enable signal to the write enable line to turn the first pass transistor off;        applying the complementary read enable signal to the read enable line to turn the second pass transistor on; and,        initially applying the pre - charge enable signal to the pre - charge enable line to initially turn the pre - charge transistor on, applying a logical complement of the precharge enable signal to the pre - charge enable line to turn the pre - charge transistor off for a brief time interval, and applying the pre - charge enable signal to the pre - charge enable line to turn the pre - charge transistor on,        while reading data from the bit cell onto the read bus without simultaneously writing data on the write bus into the bit cell.      
     
     
       34. A memory array, comprising:
   a plurality of bit cells, at least one bit cell comprising      a pair of inverters, wherein the pair of inventors comprise a first storage node and a second storage node,        a first pass transistor coupled between the first storage node and a write bus,        a write enable line coupled to a switching terminal of the first pass transistor,        a second pass transistor coupled between the second storage node and a read bus, and        a read enable line coupled to a switching terminal of the second pass transistor;          a precharge transistor coupled to the read bus; and        a precharge enable signal coupled to a switching terminal of the precharge transistor.      
     
     
       35. The memory array of  claim 34 , wherein for said at least one bit cell:
   a first inverter of the pair of inverters comprises a PMOS pull - up transistor and an NMOS pull - down transistor, and further wherein the pull - up transistor and the pull - down transistor of the first inverter define the first storage node;        a second inverter of the pair of inverters comprises a PMOS pull - up transistor and an NMOS pull - down transistor, and further wherein the pull - up transistor and the pull - down transistor of the second inverter defined the second storage node; and        the first pass transistor comprises an NMOS transistor, the second pass transistor comprises a PMOS transistor, and the precharge transistor comprises an NMOS transistor.      
     
     
       36. The memory array of  claim 35 , wherein for said at least one bit cell each of the inverters further comprises series- connected terminals defining one of the storage nodes, the series - connected terminals further comprising:      drain terminals of the respective inverter pull - up and pull - down transistors coupled together,        a logically high voltage reference signal applied to a source terminal of each one of the pull - up transistors,        a logically low voltage reference signal applied to a source terminal of each one of the pull-down transistors,        a switching terminal of the first inverter pull - up transistor coupled to a switching terminal of the first inverter pull - down transistor,        a switching terminal of the second inverter pull - up transistor coupled to a switching terminal of the second inverter pull - down transistor,        the first inverter pull - up and pull - down transistor switching terminals further coupled to the second inverter series - connected terminals,        the second inverter pull - up and pull - down transistor switching terminals further coupled to the first inverter series - connected terminals,        a source - to - drain path of the first pass transistor coupled between the write bus and the first storage node,        a source - to - drain path of the second pass transistor coupled between the read bus and the second storage node, and        a source - to - drain path of the pre - charge transistor coupled between the read bus and the logic low voltage reference signal source.      
     
     
       37. The memory array of  claim 34 , further comprising, for at least one row, a driver capable of:
   logically combining decoded first and second read signals to produce a read enable signal;        logically inverting the read enable signal to produce a complementary read enable signal;        applying the complementary read enable signal to the read enable line to turn the second pass transistor on;        logically combining a write strobe signal with the read enable signal to produce a write enable signal;        applying the write enable signal to the write enable line to turn the first pass transistor on;        if the pre - charge transistor is off, applying a pre - charge enable signal to the pre - charge enable line to turn the precharge transistor on; and,        if the pre - charge transistor is on, applying the pre - charge enable signal to the pre - charge enable line to keep the precharge transistor turned on;        while concurrently:      writing data on the write bus into the bit cell;        reading data from the bit cell onto the read bus; and,        maintaining the read bus in a logically low state.        
     
     
       38. A memory array as defined in  claim 37 , wherein the driver is further capable of:
   applying a logical complement of the write enable signal to the write enable line to turn the first pass transistor off;        applying the complementary read enable signal to the read enable line to turn the second pass transistor on; and,        initially applying the pre - charge enable signal to the pre - charge enable line to initially turn the pre - charge transistor on, applying a logical complement of the pre - charge enable signal to the pre - charge enable line to turn the pre - charge transistor off for a brief time interval, and applying the pre - charge enable signal to the pre - charge enable line to turn the pre - charge transistor on,        while reading data from the bit cell onto the read bus without simultaneously writing data on the write bus into the bit cell.      
     
     
       39. A method of writing a binary digit value asserted on a write bus into a memory bit cell, the bit cell comprising first and second storage nodes, a first pass transistor coupled between the write bus and the first storage node, a second pass transistor coupled between a read bus and the second storage node, the first pass transistor further coupled to a write enable line and capable of controllably switching the first pass transistor to be one of on and off, the second pass transistor further coupled to a read enable line and capable of controllably switching the second pass transistor to be one of on and off, and a pre- charge transistor coupled between the read bus and a logically low voltage reference signal source, the method comprising:      turning the first pass transistor on;        turning the second pass transistor on;        if the pre - charge transistor is off, turning the pre - charge transistor on; and,        if the pre - charge transistor is on, keeping the pre - charge transistor turned on.      
     
     
       40. The method of  claim 39 , wherein the bit cell further comprises first and second cross- coupled inverters defining the first and second storage nodes.    
     
     
       41. A method of reading onto a read bus a binary digit value stored in a memory bit cell, the bit cell comprising first and second inverters defining first and second storage nodes, a first pass transistor coupled between the write bus and the first storage node, a second pass transistor coupled between a read bus and the second storage node, the first pass transistor further coupled to a write enable line and capable of controllably switching the first pass transistor to be one of on and off, the second pass transistor further coupled to a read enable line and capable of controllably switching the second pass transistor to be one of on and off, and a pre- charge transistor coupled between the read bus and a logic low voltage reference signal source, the method comprising:      turning the first pass transistor off;        turning the second pass transistor on; and,        initially turning the pre-charge transistor on, then turning the pre - charge transistor off for a brief interval, then turning the pre - charge transistor on.      
     
     
       42. The method of  claim 41 , wherein the bit cell further comprises first and second cross- coupled inverters defining the first and second storage nodes.    
     
     
       43. A memory bit cell comprising:
   first and second storage nodes;        a first pass transistor coupled between a read/write bus and the first storage node; and        a second pass transistor coupled between a logically low voltage reference signal source and the second storage node,        the first pass transistor further coupled to a read/write enable line wherein the read/write enable line is capable of controllably switching the first pass transistor to be one of on and off,        the second pass transistor further coupled to a write assist line wherein the write assist line is capable of controllably switching the second pass transistor to be one of on and off,        wherein one of the first and second pass transistors comprises an NMOS transistor and the other one of the first and second pass transistors comprises a PMOS transistor.      
     
     
       44. The memory bit cell of  claim 43 , wherein the memory bit cell further comprises first and second inverters defining first and second storage nodes, and wherein:
   the first inverter further comprises a first pull - up transistor and a first pull - down transistor defining the first storage node;        the second inverter further comprises a second pull - up transistor and a second pull - down transistor defining the second storage node;        the pull - down transistors and the first pass transistor comprise NMOS transistors; and,        the pull - up transistors and the second pass transistor comprise PMOS transistors.      
     
     
       45. The memory bit of  claim 44 , wherein the first pull- up transistor and the first pull - down transistor comprise series - connected terminals defining the first storage node,      wherein the second pull - up transistor and the second pull - down transistor comprise series - connected terminals defining the second storage node,        wherein the series - connected terminals further comprise drain terminals of the respective inverter pull - up and pull - down transistors,        wherein a logically high voltage reference signal is applied to a source terminal of each one of the pull - up transistors and the logically low voltage reference signal is applied to a source terminal of each one of the pull - down transistors,        wherein a switching terminal of the first inverter pull - up transistor is coupled to a switching terminal of the first inverter pull - down transistor and a switching terminal of the second inverter pull - up transistor is coupled to a switching terminal of the second inverter pull - down transistor,        wherein the first inverter pull - up and pull - down transistor switching terminals are further coupled to the second inverter series - connected terminals and the second inverter pull - up and pull - down transistor switching terminals are further coupled to the first inverter series - connected terminals,        wherein a source - to - drain path of the first transistor is coupled between the read/write bus and the first storage node and a source - to - drain path of the second pass transistor is coupled between the logic low voltage reference signal source and the second storage node, and        wherein a switching terminal of the first pass transistor is coupled to the read/write enable line, and a switching terminal of the second pass transistor is coupled to the write assist line.      
     
     
       46. The memory bit cell of  claim 45 , further comprising circuitry capable of:
   logically combining decoded first and second read signals to produce a read/write enable signal;        applying the read/write enable signal to the read/write enable line to turn the first pass transistor on;        logically combining a write strobe signal with the read/write enable signal to produce a write assist signal; and,        applying the write assist signal to the write assist line to turn the second pass transistor on;        while performing one of:      writing data on the read/write bus into the bit cell; and        reading data from the bit cell onto the read/write bus.        
     
     
       47. A multiple- row and multiple - column memory array comprising:      a plurality of bit cells, at least one bit cell comprising:      first and second storage nodes;        a first pass transistor coupled between a read/write bus and the first storage node; and        a second pass transistor coupled between a logically low voltage reference signal source and the second storage node,        the first pass transistor further coupled to a read/write enable line wherein the read/write enable line is capable of controllably switching the first pass transistor to be one of on and off,        the second pass transistor further coupled to a write assist line wherein the write assist line is capable of controllably switching the second pass transistor to be one of on and off,        wherein one of the first and second pass transistors comprises an NMOS transistor and the other one of the first and second pass transistors comprises a PMOS transistor.        
     
     
       48. The memory array of  claim 47 , wherein said at least one bit cell further comprises first and second inverters cross- coupled to define first and second storage nodes, and wherein:      the first inverter further comprises a first pull - up transistor and a first pull - down transistor having series - connected terminals defining the first storage node;        the second inverter further comprises a second pull - up transistor and a second pull - down transistor having series - connected terminals defining the second storage node;        the pull - down transistors and the first pass transistors are NMOS transistors; and,        the pull - up transistors and the second pass transistors are PMOS transistors.      
     
     
       49. The memory array of  claim 48 , wherein the series- connected terminals further comprise drain terminals of the respective inverter pull - up and pull - down transistors,      wherein the logic high voltage reference signal is applied to a source terminal of each one of the pull - up transistors and the logic low voltage reference signal is applied to a source terminal of each one of the pull - down transistors,        wherein a switching terminal of the first inverter pull - up transistor is coupled to a switching terminal of the first inverter pull - down transistor and a switching terminal of the second inverter pull - up transistor is coupled to a switching terminal of the second inverter pull - down transistor,        wherein the first inverter pull - up and pull - down transistor switching terminals are further coupled to the second inverter series - connected terminals and the second inverter pull - up and pull - down transistor switching terminals are further coupled to the first inverter series - connected terminals,        wherein a source - to - drain path of the first pass transistor is coupled between the read/write bus and the first storage node and a source - to - drain path of the second pass transistor is coupled between the logic low voltage reference signal source and the second storage node, and        wherein a switching terminal of the first pass transistor is coupled to the read/write enable line, and a switching terminal of the second pass transistor is coupled to the write assist line.      
     
     
       50. The memory array of  claim 47 , further comprising, for each row, a driver capable of:
   logically combining decoded first and second read signals to produce a read/write enable signal;        applying the read/write enable signal to the read/write enable line to turn on the first pass transistor in each bit cell in the row;        logically combining a write strobe signal with the read/write enable signal to produce a write assist signal; and,        applying the write assist signal to the write assist line to turn on the second pass transistor in each bit cell in the row;        while performing one of:      writing data on the read/write bus into the bit cell; and        reading data from the bit cell onto the read/write bus.        
     
     
       51. A method of writing a binary digit value asserted on a read/write bus into a memory bit cell, the bit cell comprising first and second storage nodes, a first pass transistor coupled between the read/write bus and the first storage node, a second pass transistor coupled between a logically low voltage reference signal source and the second storage node, the first pass transistor further coupled to a read/write enable line and capable of controllably switching the first pass transistor to be one of on and off, the second pass transistor further coupled to a write assist line and capable of controllably switching the second pass transistor to be one of on and off, the method comprising:
   turning the first and second pass transistors on.      
     
     
       52. The method of  claim 51 , wherein the bit cell further comprises first and second inverters cross- coupled to define first and second storage nodes.    
     
     
       53. A method of reading onto a read/write bus a binary digit value stored in a memory bit cell, the bit cell comprising first and second storage nodes, a first pass transistor coupled between the read/write bus and the first storage node, a second pass transistor coupled between a logically low voltage reference signal source and the second storage node, the first pass transistor further coupled to a read/write enable line and capable of controllably switching the first pass transistor to be one of on and off, the second pass transistor further coupled to a write assist line and capable of controllably switching the second pass transistor to be one of on and off, the method comprising:
   turning the first pass transistor on and turning the second pass transistor off.      
     
     
       54. The method of  claim 53 , wherein the bit cell further comprises first and second inverters cross- coupled to define first and second storage nodes.    
     
     
       55. A memory array comprising a plurality of pairs of bit cells, at least one pair of bit cells comprising:
   first and second inverters defining first and second storage nodes, a first pass transistor coupled between a read/write bus and the first storage node, a second pass transistor coupled between a logically low voltage reference signal source and the second storage node, the first pass transistor further coupled to a first read/write enable line and capable of controllably switching the first pass transistor to be one of on and off, the second pass transistor further coupled to a write assist line and capable of controllably switching the second pass transistor to be one of on and off, one of the first and second pass transistors comprising an NMOS transistor and the other one of the first and second pass transistors comprising the PMOS transistor; and        third and fourth inverters defining third and fourth storage nodes, a third pass transistor coupled between the read/write bus and the third storage node, a fourth pass transistor coupled between the logically low voltage reference signal source and the fourth storage node, the third pass transistor further coupled to a second read/write enable line and capable of controllably switching the third pass transistor to be one of on and off, the fourth pass transistor further coupled to the write assist line and capable of controllably switching the fourth pass transistor to be one of on and off, one of the third and fourth pass transistors comprising an NMOS transistor and the other one of the third and fourth pass transistors comprising a PMOS transistor.      
     
     
       56. The memory array of  claim 55 , wherein the first and second inverters are cross- coupled to define the first and second storage nodes, and wherein the third and fourth inverters are cross - coupled to define the third and fourth storage nodes.    
     
     
       57. The memory array of  claim 55 , wherein the first and third pass transistors comprise NMOS transistors and the second and fourth pass transistors comprise PMOS transistors.  
     
     
       58. A memory array comprising a plurality of pairs of bit cells, at least one pair of bit cells comprising:
   first and second inverters defining first and second storage nodes, a first pass transistor coupled between a first read/write bus and the first storage node, a second pass transistor coupled between a logic low voltage reference signal source and the second storage node, the first pass transistor further coupled to a read/write enable line and capable of controllably switching the first pass transistor to be one of on and off, the second pass transistor further coupled to a write assist line and capable of controllably switching the second pass transistor to be one of on and off, one of the first and second pass transistors comprising an NMOS transistor and the other one of the first and second pass transistors comprising a PMOS transistor; and,        third and fourth inverters defining third and fourth storage nodes, a third pass transistor coupled between a second read/write bus and the third storage node, a fourth pass transistor coupled between the logic low voltage reference signal source and the fourth storage node, the third pass transistor further coupled to the read/write enable line and capable of controllably switching the third pass transistor to be one of on and off, the fourth pass transistor further coupled to the write assist line and capable of controllably switching the fourth pass transistor to be one of on and off, one of the third and fourth pass transistors comprising an NMOS transistor and the other one of the third and fourth pass transistors comprising a PMOS transistor.      
     
     
       59. The memory array of  claim 58 , wherein the first and second inverters are cross- coupled to define the first and second storage nodes, and wherein the third and fourth inverters are cross - coupled to define the third and fourth storage nodes.    
     
     
       60. The memory array of  claim 58 , wherein the first and third pass transistors comprise NMOS transistors and the second and fourth pass transistors comprise PMOS transistors.  
     
     
       61. A memory array comprising a plurality of quadruplets of bit cells, at least one quadruplet of bit cells comprising:
   first and second inverters defining first and second storage nodes, a first pass transistor coupled between a first read/write bus and the first storage node, a second pass transistor coupled between a logic low voltage reference signal source and the second storage node, the first pass transistor further coupled to a first read/write enable line and capable of controllably switching the first pass transistor to be one of on and off, the second pass transistor further coupled to a write assist line and capable of controllably switching the second pass transistor to be one of on and off, one of the first and second pass transistors comprising an NMOS transistor and the other one of the first and second pass transistors comprising a PMOS transistor;        third and fourth inverters defining third and fourth storage nodes, a third pass transistor coupled between the first read/write bus and the third storage node, a fourth pass transistor coupled between the logic low voltage reference signal source and the fourth storage node, the third pass transistor further coupled to a second read/write enable line and capable of controllably switching the third pass transistor to be one of on and off, the fourth pass transistor further coupled to the write assist line and capable of controllably switching the fourth pass transistor to be one of on and off, one of the third and fourth pass transistors comprising an NMOS transistor and the other one of the third and fourth pass transistors comprising a PMOS transistor;        fifth and sixth inverters defining fifth and sixth storage nodes, a fifth pass transistor coupled between a second read/write bus and the fifth storage node, a sixth pass transistor coupled between the logic low voltage reference signal source and the sixth storage node, the fifth pass transistor further coupled to the first read/write enable line and capable of controllably switching the fifth pass transistor to be one of on and off, the sixth pass transistor further coupled to the write assist line and capable of controllably switching the sixth pass transistor to be one of on and off, one of the fifth and sixth pass transistors comprising an NMOS transistor and the other one of the fifth and sixth pass transistors comprising a PMOS transistor; and,        seventh and eighth inverters defining seventh and eighth storage nodes, a seventh pass transistor coupled between the second read/write bus and the seventh storage node, an eighth pass transistor coupled between the logic low voltage reference signal source and the eighth storage node, the seventh pass transistor further coupled to the second read/write enable line and capable of controllably switching the seventh pass transistor to be one of on and off, the eighth pass transistor further coupled to the write assist line and capable of controllably switching the eighth pass transistor to be one of on and off, one of the seventh and eighth pass transistors comprising an NMOS transistor and the other one of the seventh and eighth pass transistors comprising a PMOS transistor.      
     
     
       62. The memory array of  claim 61 , wherein the first and second inverters are cross- coupled to define first and second storage nodes, wherein the third and fourth inverters are cross - coupled to define the third and fourth storage nodes, wherein the fifth and sixth inverters are cross - coupled to define the fifth and sixth storage nodes, and wherein the seventh and eighth inverters are cross - coupled to define the seventh and eighth storage nodes.    
     
     
       63. The memory array of  claim 61 , wherein the first, third, fifth and seventh pass transistors comprise NMOS transistors and the second, fourth, sixth and eighth pass transistors comprise PMOS transistors.  
     
     
       64. The memory of  claim 29 , wherein the pair of inverters comprise cross- coupled invertors.   
     
     
       65. The memory array of  claim 34 , wherein the pair of inverters comprise cross- coupled invertors.