Output buffer circuit and semiconductor memory using the same

Abstract

An output buffer circuit of the present invention includes a plurality of unit circuits in each of which a pull-up transistor controlled by a first input signal is connected between a high-potential power supply and common node, and a pull-down transistor controlled by a second input signal is connected between the common node and a low-potential power supply, an output terminal connected to a common connecting point of the common nodes of the plurality of unit circuits, and first resistors formed respectively between the common nodes of the plurality of unit circuits and the common connecting point.

1. An output buffer circuit comprising:
 a plurality of unit circuits in each of which a pull-up transistor controlled by a first input signal is connected between a high-potential power supply and common node, and a first pull-down transistor controlled by a second input signal and a second pull-down transistor controlled by a third input signal are connected in series between said common node and a low-potential power supply;  
 an output terminal connected to a common connecting point of said common nodes of said plurality of unit circuits;  
 first resistors formed respectively between said common nodes of said plurality of unit circuits and said common connecting; and  
 second resistors formed respectively between said high-potential power supply and pull-up transistor and between said pull-down transistor and low-potential power supply in each of said plurality of unit circuits.  
 
     
     
       2. An output buffer circuit comprising:
 a plurality of unit circuits in each of which a plurality of pull-up transistors controlled by an input signal are connected in series between a high-potential power supply and common nodes, and a plurality of pull-down transistors controlled by an input signal are connected in series between said common nodes and a low-potential power supply;  
 an output terminal connected to a common connecting point of said common nodes of said plurality of unit circuits; and  
 first resistors formed respectively between said common nodes of said plurality of unit circuits and said common connecting; and third resistors formed respectively between said pull-up transistors and common nodes and between said common nodes and pull-down transistors in each of said plurality of unit circuits.  
 
     
     
       3. The output buffer circuit according to  claim 1 , wherein said plurality of second resistors formed respectively between said high-potential power supply and pull-up transistor and between said pull-down transistor and low-potential power supply have the same resistance. 
     
     
       4. The output buffer circuit according to  claim 2 , wherein said plurality of third resistors formed respectively between said pull-up transistors and common nodes and between said common nodes and pull-down transistors have the same resistance. 
     
     
       5. The output buffer circuit according to  claim 2 , wherein said plurality of first resistors formed between said common nodes and output terminal have the same resistance. 
     
     
       6. The output buffer circuit according to  claim 2 , wherein each of said pull-up and pull-down transistors is a MIS transistor. 
     
     
       7. The output buffer circuit according to  claim 2 , wherein said plurality of pull-up transistors have the same gate length and the same gate width, and said plurality of pull-down transistors have the same gate length and the same gate width. 
     
     
       8. The output buffer circuit according to  claim 2 , wherein said resistor is selected from the group consisting of a metal film, composite metal film, metal cermet film, polysilicon film, diffusion layer, and transistor. 
     
     
       9. A semiconductor memory comprising:
 a plurality of memory cells;  
 a plurality of terminals including an output terminal; and  
 an output buffer circuit positioned adjacent to said memory cell, said output buffer circuit comprising a plurality of unit circuits in each of which a pull-up transistor controlled by a first input signal is connected between a high-potential power supply and common node and a pull-down transistor controlled by a second input signal is connected between said common node and a low-potential power supply, and comprising first resistors connected respectively between said common nodes of said plurality of unit circuits and a common connecting point of said common nodes,  
 wherein said first resistors are formed between said output buffer circuit and output terminal, and  
 wherein, if the number of said first resistors is an even number, said first resistors are symmetrically arranged with respect to a central line of said output buffer circuit and output terminal, and have the same value, the same size, and the same shape.  
 
     
     
       10. A semiconductor memory comprising:
 a plurality of memory cells;  
 a plurality of terminals including an output terminal; and  
 an output buffer circuit positioned adjacent to said memory cell, said output buffer circuit comprising a plurality of unit circuits in each of which a pull-up transistor controlled by a first input signal is connected between a high-potential power supply and common node and a pull-down transistor controlled by a second input signal is connected between said common node and a low-potential power supply, and comprising first resistors connected respectively between said common nodes of said plurality of unit circuits and a common connecting point of said common nodes,  
 wherein said first resistors are formed between said output buffer circuit and output terminal and said first resistors are formed on at least not less than one of three sides of said output terminal, which do not oppose said output buffer circuit.  
 
     
     
       11. The semiconductor memory according to  claim 10 , wherein if the number of first resistors is two, said first resistors are symmetrically arranged in portions of said output terminal, which do not oppose said output buffer circuit, and have the same value, the same size, and the same shape. 
     
     
       12. A circuit, comprising:
   a plurality of terminals including an output terminal; and        an output buffer circuit connected to one of said terminals, comprising:      a first circuit having a first pull - up transistor connected between a power supply potential and a first node and a first pull - down transistor connected between said first node and a low power supply potential,        a second circuit having a second pull - up transistor connected between said power supply potential and a second node and a second pull - down transistor connected between said second node and said low power supply potential,        a first resistor connected between said first pull - up transistor and said first node,        a second resistor connected between said first pull - down transistor and said first node,        a third resistor connected between said second pull - up transistor and said second node, and        a fourth resistor connected between said second pull - down transistor and said second node.       
     
     
       13. The circuit according to  claim 12 , comprising:
   said first node connected to said second node at a third node; and        said third node connected to said output terminal.     
     
     
       14. The circuit according to  claim 13 , comprising:
   a fifth resistor connected between said third node and said output terminal.     
     
     
       15. The circuit according to  claim 13 , comprising:
   a first wiring connected between said first node and said third node;        a second wiring connected between said second node and said third node; and        a third wiring connected between said third node and said output terminal.     
     
     
       16. The circuit according to  claim 13 , comprising:
   a fifth resistor connected between said first node and said third node; and        a sixth resistor connected between said second node and said third node.     
     
     
       17. The circuit according to  claim 16 , comprising:
   a first wiring connected between said third node and said output terminal.     
     
     
       18. The circuit according to  claim 12 , comprising:
   a fifth resistor connected between said first node and said output terminal; and        a sixth resistor connected between said second node and said output terminal.     
     
     
       19. The circuit according to  claim 12 , wherein each of said first through fourth resistors has substantially the same value. 
     
     
       20. The circuit according to  claim 12 , wherein each of said first and second pull- up transistors has the substantially the same gate width and gate length.   
     
     
       21. The circuit according to  claim 12 , wherein each of said first and second pull- down transistors has the substantially the same gate width and gate length.   
     
     
       22. The circuit according to  claim 12 , wherein each of said first and second pull- up transistors and said first and second pull - down transistors has the substantially the same gate width and gate length.   
     
     
       23. The circuit according to  claim 12 , comprising:
   a first transistor connected between said first pull - down transistor and said low power supply potential; and        a second transistor connected between said second pull - down transistor and said low power supply potential.     
     
     
       24. The circuit according to  claim 12 , wherein said resistors are selected from the group consisting of a transistor, a metal film, a polysilicon film, and a diffusion layer. 
     
     
       25. The circuit according to  claim 12 , wherein said output buffer circuit comprises:
   a third circuit having a third pull - up transistor connected between said power supply potential and a third node and a third pull - down transistor connected between said third node and a low power supply potential,        a fourth circuit having a fourth pull - up transistor connected between said power supply potential and a fourth node and a fourth pull - down transistor connected between said fourth node and said low power supply potential;        a fifth resistor connected between said third pull - up transistor and said third node;        a sixth resistor connected between said third pull - down transistor and said third node;        a seventh resistor connected between said fourth pull - up transistor and said fourth node; and        an eighth resistor connected between said fourth pull - down transistor and said fourth node.     
     
     
       26. The circuit according to  claim 25 , comprising:
   said first, second, third and fourth nodes each being connected to a fifth node; and        said fifth node being connected to said output terminal.     
     
     
       27. The circuit according to  claim 26 , comprising:
   a ninth resistor connected between said fifth node and said output terminal.     
     
     
       28. The circuit according to  claim 26 , comprising:
   a first wiring connected between said first node and said fifth node;        a second wiring connected between said second node and said fifth node;        a third wiring connected between said third node and said fifth node;        a fourth wiring connected between said fourth node and said fifth node; and        a fifth wiring connected between said fifth node and said output terminal.     
     
     
       29. A circuit as recited in  claim 26 , comprising:
   a ninth resistor connected between said first node and said fifth node;        a tenth resistor connected between said second node and said fifth node;        an eleventh resistor connected between said third node and said fifth node; and        a twelfth resistor connected between said fourth node and said fifth node.     
     
     
       30. The circuit according to  claim 29 , comprising:
   a first wiring connected between said fifth node and said output terminal.     
     
     
       31. The circuit according to  claim 25 , comprising:
   a ninth resistor connected between said first node and said output terminal;        a tenth resistor connected between said second node and said output terminal;        an eleventh resistor connected between said third node and said output terminal; and        a twelfth resistor connected between said fourth node and said output terminal.     
     
     
       32. The circuit according to  claim 25 , wherein each of said first through eighth resistors has substantially the same value. 
     
     
       33. The circuit according to  claim 25 , wherein each of said first through fourth pull- up transistors has the substantially the same gate width and gate length.   
     
     
       34. The circuit according to  claim 25 , wherein each of said first through fourth pull- down transistors has the substantially the same gate width and gate length.   
     
     
       35. The circuit according to  claim 25 , wherein each of said first through fourth pull- up transistors and said first through fourth pull - down transistors has the substantially the same gate width and gate length.   
     
     
       36. The circuit according to  claim 25 , comprising:
   a first transistor connected between said first pull - down transistor and said low power supply potential;        a second transistor connected between said second pull - down transistor and said low power supply potential;        a third transistor connected between said third pull - down transistor and said low power supply potential; and        a fourth transistor connected between said fourth pull - down transistor and said low power supply potential.     
     
     
       37. The circuit according to  claim 25 , wherein said resistors are selected from the group consisting of a transistor, a metal film, a polysilicon film, and a diffusion layer. 
     
     
       38. The circuit according to  claim 12 , comprising:
   a memory having memory transistors,        a gate length of said transistors in said buffer circuit being larger than a gate length of said memory transistors.     
     
     
       39. A circuit, comprising:
   an output terminal;        a first circuit having a first p - type transistor connected between a power supply potential and a first node and a first n - type transistor connected between said first node and a low power supply potential, and        a second circuit having a second p - type transistor connected between said power supply potential and a second node and a second n - type transistor connected between said second node and said low power supply potential;        a first resistor connected between said first p - type transistor and said first node;        a second resistor connected between said first n - type transistor and said first node;        a third resistor connected between said second p - type transistor and said second node; and        a fourth resistor connected between said second n - type transistor and said second node.     
     
     
       40. The circuit according to  claim 39 , comprising:
   a memory having memory transistors,        a gate length of said transistors in said first and second circuits being larger than a gate length of said memory transistors.     
     
     
       41. A circuit, comprising:
   a plurality of terminals including an output terminal; and        an output buffer circuit connected to one of said terminals, comprising:      a first circuit having first and second p - type transistors connected in series between a power supply potential and a first node and first and second n - type transistors connected in series between said first node and a low power supply potential,        a second circuit having third and fourth p - type transistors connected in series between said power supply potential and a second node and third and fourth n - type transistors connected in series between said second node and said low power supply potential,        a first resistor connected between said first node and said output terminal, and        a second resistor connected between said second node and said output terminal.       
     
     
       42. The circuit according to  claim 41 , wherein each of said first and second resistors has substantially the same value. 
     
     
       43. The circuit according to  claim 41 , wherein each of said first, second, third and fourth p- type transistors has the substantially the same gate width and gate length.   
     
     
       44. The circuit according to  claim 41 , wherein each of said first, second, third and fourth n- type transistors has the substantially the same gate width and gate length.   
     
     
       45. The circuit according to  claim 41 , wherein each of said first, second, third and fourth p- type and n - type transistors has the substantially the same gate width and gate length.   
     
     
       46. The circuit according to  claim 41 , comprising:
   a first end of said first resistor connected to said first node and a second end connected to a third node;        a first end of said second resistor connected to said second node and a second end of said second resistor connected to a third node; and        said third node connected to said output terminal.     
     
     
       47. The circuit according to  claim 41 , comprising:
   a memory having memory transistors,        a gate length of said transistors in said buffer circuit being larger than a gate length of said memory transistors.