Digital signal coding apparatus, digital signal decoding apparatus, digital signal arithmetic coding method and digital signal arithmetic decoding method

Abstract

In a bit stream syntax containing compressed video slice data for compressed video data of a slice structure, a slice header for compressed video slice data has attached thereto a slice start code, a register reset flag indicating whether a register value, which designates a status of a codeword occurring in an arithmetic coding process, should be reset in the next transmission unit, an initial register value which indicates a register value to be used to start arithmetic coding/decoding to build/decompose the next transmission unit, only when the register reset flag indicates that the register should not be reset.

1. A digital signal coding apparatus for partitioning a digital signal into predetermined units for compression coding, comprising:
 an arithmetic coding unit for compressing, by arithmetic coding, the digital signal partitioned into the units, wherein said arithmetic coding unit multiplexes information representing an arithmetic coding status, occurring when a given transmission unit has been coded, into  with data constituting a subsequent transmission unit.  
 
     
     
       2. The digital signal coding apparatus according to  claim 1 , wherein said arithmetic coding unit arithmetically codes the digital signal partitioned into the units, by determining a probability of occurrence of coding symbols, based on dependence of the digital signal coded on the signal included in one or a plurality of adjacent transmission unit. 
     
     
       3. The digital signal coding apparatus according to  claim 2 , wherein said arithmetic coding unit learns the probability of occurrence by counting a frequency of occurrence of coding symbols. 
     
     
       4. The digital signal coding apparatus according to  claim 1 , wherein the information representing the arithmetic coding status includes a register reset flag indicating whether a register value designating an arithmetic coding process is reset or not and an initial register value included in the information only when the register value is not reset. 
     
     
       5. A digital signal coding apparatus for partitioning a digital signal into predetermined units for compression coding, comprising:
 an arithmetic coding unit for compressing, by arithmetic coding, the digital signal partitioned into the units, wherein said arithmetic coding unit determines a probability of occurrence of coding symbols, based on dependence of the digital signal coded on the signal included in one or a plurality of adjacent transmission units, learns the probability of occurrence by counting a frequency of occurrence of coding symbols and multiplexes information representing a probability learning status, occurring when a given transmission unit has been coded, into  with data constituting a subsequent transmission unit.  
 
     
     
       6. The digital signal coding apparatus according to  claim 5 , wherein the information representing the probability learning status is information representing a context model status, a context model being a model that defines dependence of the probability of occurrence of data symbols on information that causes variation in the probability. 
     
     
       7. The digital signal coding apparatus according to  claim 1 , wherein the digital signal is a video signal and the transmission unit is a slice constituted by one or a plurality of macroblocks in a video frame. 
     
     
       8. The digital signal coding apparatus according to  claim 1 , wherein the digital signal is a video signal and the transmission unit is constructed by collecting coding data in a slice according to a type of the coding data. 
     
     
       9. The digital signal coding apparatus according to  claim 1 , wherein the digital signal is a video signal and the transmission unit is a video frame. 
     
     
       10. A digital signal coding apparatus for outputting a bitstream containing coded data of a digital signal of a predetermined unit, comprising:
   an arithmetic coding unit for compressing, by arithmetic coding, the digital signal of the predetermined unit, and        a header multiplexing unit for multiplexing information representing an arithmetic coding status to be used for arithmetic decoding of the predetermined unit, with the bitstream as an element of header information associated with said predetermined unit.     
     
     
       11. A digital signal coding method for outputting a bitstream containing coded data of a digital signal of a predetermined unit, comprising:
   compressing, by arithmetic coding, the digital signal of the predetermined unit, and multiplexing information representing an arithmetic coding status to be used for arithmetic decoding of the predetermined unit, with the bitstream as an element of header information associated with said predetermined unit.