Semiconductor memory

Abstract

A semiconductor memory having a memory cell structure capable of reducing soft error without complicating a circuit configuration. Specifically, an inverter (I1) consists of a NMOS transistor (N1) and a PMOS transistor (P1), and an inverter (I2) consists of a NMOS transistor (N2) and a PMOS transistor (P2). The inverters (I1, I2) are subjected to cross section. The NMOS transistor (N1) is formed within a P well region (PW0), and the NMOS transistor (N2) is formed within a P well region (PW1). The P well regions (PW0, PW1) are oppositely disposed with an N well region (NW) interposed therebetween.

What is claimed is:  
     
       1. A semiconductor memory comprising:
 a memory cell having first and second storage terminals storing information of logic levels complementary to each other;  
 a power supply wiring supplying a predetermined power supply voltage to said memory cell;  
 first and second pairs of bit lines each electrically connected to said first and second storage terminals of said memory cell, when selected; and  
 first and second word lines connected to said memory cell, said first pair of bit lines connected to said memory cell and at least reading out data stored at said first and second storage terminals from said memory cell in response to a signal on said first word line, and said second pair of bit lines connected to said memory cell and at least reading out data stored at said first and second storage terminals from said memory cell in response to a signal on said second word line, wherein 
 said first and second pairs of bit lines and said power supply wiring are provided in parallel to each other, with said power supply wiring interposed between said first and second pairs of bit lines.  
 
 
     
     
       2. The semiconductor memory according to  claim 1 , further comprising:
 first and second ground wirings each supplying a predetermined ground potential to said memory cell, wherein 
 said first pair of bit lines and said first ground wiring are provided in parallel to each other, with said first ground wiring interposed between said first pair of bit lines, and  
 said second pair of bit lines and said second ground wiring are provided in parallel to each other, with said second ground wiring interposed between said second pair of bit lines.  
 
 
     
     
       3. The semiconductor memory according to  claim 1 , wherein
 said memory cell is formed on first and second P wells and an N well interposed between said first and second P wells in a first direction, and said power supply wiring extending along a second direction vertical to said first direction is formed on said N well.  
 
     
     
       4. A semiconductor device comprising a two- port static memory cell including:      a first inverter having an input connected to a first storage node and an output connected to a second storage node;        a second inverter having an input connected to said second storage node and an output connected to said first storage node;        a first transistor of first conductivity type having one end connected to said first storage node, the other end connected to a first bit line provided for a first port, and a gate electrode connected to a first word line;        a second transistor of said first conductivity type having one end connected to said first storage node, the other end connected to a second bit line provided for a second port and a gate electrode connected to a second word line;        a third transistor of said first conductivity type having one end connected to said second storage node, the other end connected to a third bit line provided for said first port and a gate electrode connected to said first word line; and        a fourth transistor of said first conductivity type having one end connected to said second storage node, the other end connected to a fourth bit line provided for said second port and a gate electrode connected to said second word line, wherein        said first and second word lines are arranged in parallel to each other,        said two - port static memory cell is divided into a first region of second conductivity type, a second region of said first conductivity type and a third region of said second conductivity type, arranged in this order in a direction of extension of said first and second word lines, said first to third regions respectively having transistors formed therein,        said first transistor, said third transistor and a fifth transistor of said first conductivity type constituting said second inverter are arranged in said first region,        a seventh transistor of said second conductivity type constituting said second inverter and an eighth transistor of said second conductivity type constituting said first inverter are arranged in said second region, and        said second transistor, said fourth transistor and a sixth transistor of said first conductivity type constituting said first inverter are arranged in said third region.     
     
     
       5. The semiconductor device according to  claim 4 , wherein said first to fourth bit lines each are arranged to extend in a direction perpendicular to said first and second word lines. 
     
     
       6. The semiconductor device according to  claim 5 , wherein
   the gate electrodes of said first and third transistors are connected to each other to constitute a first gate electrode with an integral gate electrode pattern, and        the gate electrodes of said second and fourth transistors are connected to each other to constitute a second gate electrode with an integral gate electrode pattern.     
     
     
       7. The semiconductor device according to  claim 6 , wherein
   the gate electrodes of said fifth and seventh transistors are connected to each other to constitute a third gate electrode with an integral gate electrode pattern,        the gate electrodes of said sixth and eighth transistors are connected to each other to constitute a fourth gate electrode with an integral gate electrode pattern, and        said first to fourth gate electrodes extend in the direction of extension of said first and second word lines.     
     
     
       8. The semiconductor device according to  claim 5 , wherein
   said first and fifth transistors have their active regions connected to each other to constitute an integral active region,        said fourth and sixth transistors have their active regions connected to each other to constitute an integral active region,        said second and fifth transistors have their active regions isolated from and connected to each other through an interconnect line, and        said third and sixth transistors have their active regions isolated from and connected to each other through an interconnect line.     
     
     
       9. The semiconductor device according to  claim 8 , wherein
   said third transistor is arranged closer to said second region than said first transistor, and        said second transistor is arranged closer to said second region than said fourth transistor.     
     
     
       10. The semiconductor device according to  claim 8 , wherein
   said first transistor is arranged closer to said second region than said third transistor, and        said fourth transistor is arranged closer to said second region than said second transistor.