System and method for integrating a digital core with a switch mode power supply

Abstract

A digital core embodied within a semiconductor die that requires plural separate power supply voltage domains is situated within any of a variety of integrated circuit packaging technologies. Within the integrated circuit package including this semiconductor die also exists a switch mode DC-to-DC voltage converter, preferably a synchronous step-down regulator powering the entire integrated circuit from one supply voltage. The components contained within the integrated circuit package along with the semiconductor die include the switch mode power supply's power switching transistors, inductor core and windings, digital open-loop output voltage fixing circuitry, output capacitors and substrate for mounting said components when integrated within a packaging technology that does not already include a substrate.

1. An integrated circuit package, comprising:
 a semiconductor die of plural separate power supply voltage domains; and  
 a switch mode DC-to-DC converter, comprising:  
 wherein said switch mode DC-to-DC converter comprises: 
 an inductor core and windings;    a power switching transistor; and    an output voltage fixing circuit comprising a digital open-loop means  circuit configuration requiring no feed-forward loop and no feedback loop.    
 
     
     
       2. An integrated circuit package, comprising:
 a semiconductor die of plural separate power supply voltage domains; and  
 a switch mode DC-to-DC converter, comprising:  
 wherein said switch mode DC-to-DC converter comprises: 
 an inductor core and windings;    a power switching transistor; and    an output voltage fixing circuit,    
 wherein said semiconductor die comprises a decoder that compares an entry from a table corresponding to the present power state of said semiconductor die to a clock counter frequency divider output to determine a duty cycle and/or switching frequency of said power switching transistor for said output voltage fixing circuit.  
 
     
     
       3. The integrated circuit of  claim 2 , wherein said table of entries of clock counter values  used to determine said duty cycle is encoded within logic within  circuitry of said semiconductor die. 
     
     
       4. The integrated circuit of  claim 2 , wherein said table of entries of clock counter values  used to determine said duty cycle is contained within non-volatile memory. 
     
     
       5. The integrated circuit package of  claim 2 , wherein the  a power transistor gate-driving signal output from said semiconductor die is connected through a charge pump circuit to optimize the efficiency of the power switching transistor of said DC-to-DC converter. 
     
     
       6. The integrated circuit package of  claim 2 , further comprising a substrate of fiberglass resin epoxy of type FR 4  based  FR 4 -based laminate material for mounting components of said DC-to-DC converter components . 
     
     
       7. The integrated circuit package of  claim 6 , wherein said semiconductor die further comprises a plurality of pads from which to accept a binary number offset for fine tuning said duty cycle and/or switching frequency by modifying the value  said table entry being compared to the clock counter frequency divider in  output by said output voltage fixing circuit of said DC-to-DC converter. 
     
     
       8. The output voltage fixing  integrated circuit package of  claim 7 , wherein said binary number offset is embodied  included within fusible leads on said substrate that are electrically or mechanically trimmed or laser-trimmed at the factory . 
     
     
       9. The output voltage fixing  integrated circuit package of  claim 7 , wherein said binary number offset is embodied  included within a  an optional wire-bonding option during assembly  of said plurality of semiconductor die pads to the lead frame of said integrated circuit package. 
     
     
       10. The integrated circuit package of  claim 6 , wherein the  a power transistor gate driving  that drives signal output from said semiconductor die is connected through a trimmed delay circuit to fine tune the duty cycle of a pulse width modulator or pulse frequency modulator of the output voltage fixing circuit of said DC-to-DC converter. 
     
     
       11. The output voltage fixing  integrated circuit package of  claim 10 , wherein said trimmed delay circuit further comprises a laser-trimmed printed film resistor on the substrate that is laser-trimmed at the factory . 
     
     
       12. An integrated circuit package,  comprising,
 a substrate of fiberglass resin epoxy of type FR 4  g based laminate material for mounting: ;  
 a semiconductor die of plural separate power supply voltage domains mounted on said substrate; and  
 a switch mode DC-to-DC converter further comprising an inductor core and windings,  mounted on said substrate, wherein said switch mode DC-to-DC converter comprises:
 a power switching transistor; and  
 an output voltage fixing circuit comprising a digital open-loop means  circuit configuration requiring no feed-forward loop and no feedback loop.  
 
 
     
     
       13. The output voltage fixing  integrated circuit package of  claim 7 , wherein said binary number offset is embodied  included within a  an optional wire-bonding option during assembly  of said plurality of semiconductor die pads onto a  said substrate of fiberglass resin epoxy of type FR 4  based  FR 4 -based laminate material. 
     
     
       14. A method for design and fabrication of an integrated circuit package comprising a semiconductor die of plural separate power supply voltage domains with an integrated switch mode power supply, said method comprising steps of :
 designing a semi-custom or standard cell library based digital core and obtaining from the design automation tools power consumption estimates in various power states given known clocking rates;  
 determining switch mode power supply frequency, inductance, and duty cycles for various power states given said power consumption estimates and system clocking;  
 fabricating said semiconductor die for prototyping purposes, packaged without said integrated switch mode power supply;  
 characterizing said prototype semiconductor die for power consumption over all operating power states and environmental conditions and process variations;  
 fabricating said switch mode power supply onto final production substrates;  
 trimming the output voltage fixing circuit of said switch mode power supply after a probe test to determine the output voltages at given duty cycles versus output currents defined by said semiconductor die known characterization data; and  
 bonding and molding or sealing with epoxy said semiconductor die and power supply substrate into an integrated package.  
 
     
     
       15. The method of  claim 14 , wherein said step of trimming the output voltage fixing circuit further comprises a step of binning said final production power supply substrates into the appropriate wire-bonding assembly line to set the proper binary number offset of the output voltage fixing circuit. 
     
     
       16. The method of  claim 14 , wherein said step of trimming the output voltage fixing circuit further comprises a step of breaking fusible leads on said final production power supply substrate to set the binary number offset of the output voltage fixing circuit. 
     
     
       17. The method of  claim 14 , wherein said step of trimming the output voltage fixing circuit further comprises a step of laser trimming a printed film resistor forming a delay circuit of the output voltage fixing circuit on said final power supply substrate. 
     
     
       18. The method of  claim 14 , wherein said step of trimming the output voltage fixing circuit further comprises a step of programming a non-volatile memory with entries of clock counter values to determine duty cycle and/or switching frequency corresponding to each power state of the semiconductor die. 
     
     
       19. A method for design and fabrication of an integrated circuit package comprising a semiconductor die of plural separate power supply voltage domains with an integrated switch mode power supply, said method comprising steps of :
 designing a semi-custom or standard cell library based digital core and obtaining from the design automation tools power consumption estimates in various power states given known clocking rates;  
 determining switch mode power supply frequency, inductance, and duty cycles for various power states given said power consumption estimates and system clocking;  
 fabricating said semiconductor die for prototyping purposes, packaged without said integrated switch mode power supply;  
 characterizing said prototype semiconductor die for power consumption over all operating power states and environmental conditions and process variations;  
 fabricating said switch mode power supply onto final production substrates; and  
 bonding and molding or sealing with epoxy said semiconductor die and assembled final power supply substrate into an integrated package.  
 
     
     
       20. A semiconductor die comprising a decoder that compares an entry from a table corresponding to a present power state of said semiconductor die to a clock counter frequency divider output to determine a duty cycle and/or switching frequency of at least one power switching transistor for an output voltage fixing circuit of a switch mode DC-to-DC converter. 
     
     
       21. The semiconductor die of  claim 20 , wherein said table used to determine said duty cycle is encoded within logic circuitry of said semiconductor die. 
     
     
       22. The semiconductor die of  claim 20 , wherein said table used to determine said duty cycle is contained within non-volatile memory. 
     
     
       23. The semiconductor die of  claim 20 , further comprising:
   at least one pad from which to accept a binary number offset for fine tuning said duty cycle and/or switching frequency, wherein said fine tuning operates by modifying said table entry being compared to the clock counter frequency divider output by said output voltage fixing circuit of said DC-to-DC converter.     
     
     
       24. The semiconductor die of  claim 23 , wherein said binary offset is a binary output of at least one analog comparator. 
     
     
       25. A method of design of a power supply for an integrated circuit, comprising:
   determining a prior characterization of power consumption over all operating power states, environmental conditions, and process variations of said integrated circuit; and        providing as said power supply an output voltage fixing circuit that retains precision based on said determined power consumption characterization data of said integrated circuit.     
     
     
       26. The integrated circuit package of  claim 1 , wherein said switch mode DC-to-DC converter further comprises an inductor core and windings. 
     
     
       27. An integrated circuit package, comprising:
   a semiconductor die of plural separate power supply voltage domains; and        a switch mode DC-to-DC converter, comprising:      a power switching transistor; and        an output voltage fixing circuit comprising a digital open-loop circuit configuration that retains precision based on power consumption characterization data of said semiconductor die.       
     
     
       28. The integrated circuit package of  claim 27 , wherein said switch mode DC-to-DC converter further comprises an inductor core and windings. 
     
     
       29. The integrated circuit package of  claim 2 , wherein said decoder compares an entry from a table, said entry based on power consumption characterization data and corresponding to the present power state of said semiconductor die, to the clock counter frequency divider output to determine a duty cycle and/or switching frequency of said power switching transistor for said output voltage fixing circuit. 
     
     
       30. The integrated circuit package of  claim 12 , wherein said substrate is fiberglass resin epoxy of type FR 4 -based laminate material. 
     
     
       31. The integrated circuit package of  claim 12 , wherein said switch mode DC-to-DC converter comprises an inductor core and windings. 
     
     
       32. An integrated circuit package, comprising:
   a substrate;        a semiconductor die of plural separate power supply voltage domains mounted on said substrate; and        a switch mode DC-to-DC converter comprising:      a power switching transistor; and        an output voltage fixing circuit configured to retain precision based on power consumption characterization data of said semiconductor die.       
     
     
       33. The integrated circuit package of  claim 32 , wherein said switch mode DC-to-DC converter further comprises an inductor core and windings. 
     
     
       34. The integrated circuit package of  claim 32 , wherein said output voltage fixing circuit comprises a digital open-loop circuit configuration requiring no feed- forward loop and no feedback loop.   
     
     
       35. The integrated circuit package of  claim 32 , wherein said substrate is fiberglass resin epoxy of type FR 4 -based laminate material. 
     
     
       36. The semiconductor die of  claim 20 , wherein said table entries are based on power consumption characterization data and correspond to the present power state of said semiconductor die. 
     
     
       37. The semiconductor die of  claim 24 , wherein said at least one analog comparator enables operation of said DC-to-DC converter in an energy-saving pulse skip mode. 
     
     
       38. The integrated circuit package of  claim 2 , wherein said switch mode DC-to-DC converter further comprises an inductor core and windings.