Graphics engine command FIFO for programming multiple registers using a mapping index with register offsets

Abstract

A host writes graphics commands and data to programmable registers through a command FIFO that is read by a graphics controller or BitBlt engine. Rather than write an address and a data value for each register programmed, the host writes one address, one index, and several data values. The address points to an index register. The index is a mapping index word with several multi-bit mapping fields. Each multi-bit mapping field in the index identifies a register to be programmed with one of the data values. Since N bits are used for each mapping field, the mapping field can select one register in a bank of 2 N −1 registers. The registers in the bank can be programmed in any order, and registers can be skipped. Since only one index is stored in the command FIFO for programming several registers, less memory space and fewer bus cycles are required.

1. A graphics engine comprising:
 a command first-in-first-out FIFO for storing entries written by a host, the entries being commands and data to the graphics engine from the host, the entries including a first entry that is an index value, and a plurality of data entries, the first entry being written to an address of the command FIFO;  
 an index register, written with the index value from the first entry;  
 a selector, coupled to the index register, for selecting a multi-bit mapping field from the index register, wherein the index value contains a plurality of multi-bit mapping fields each capable of indicating a different register in a bank of programmable registers;  
 a decoder, coupled to receive the multi-bit mapping field selected by the selector from the index register, for decoding the multi-bit mapping field to indicate a selected register in the bank of programmable registers; and  
 a switching bus, coupled to transfer one of the plurality of data entries from the command FIFO to the selected register to write a data value to the selected register;  
 wherein the plurality of data entries from the command FIFO are written to several different selected registers in the bank of programmable registers by the selector selecting different multi-bit mapping fields from the index register and the decoder decoding different multi-bit mapping fields to cause the switching bus to write the data entries to the several different selected registers,  
 whereby the multi-bit mapping fields in the index register are selected and decoded to write data values to the several different selected registers in the bank of programmable registers.  
 
     
     
       2. The graphics engine of  claim 1  wherein the index value contains at least 8 multi-bit mapping fields. 
     
     
       3. The graphics engine of  claim 2  wherein each multi-bit mapping field is at least four bits;
 wherein the bank of programmable registers includes at least 15 registers that can be selected as the selected register for programming with a data value;  
 wherein the data entries include up to eight data values for programming up to 8 of the 15 registers using the entries that include the index value,  
 whereby up to eight registers in a bank of 15 registers can be programmed with one index value.  
 
     
     
       4. The graphics engine of  claim 1  wherein each multi-bit mapping field is N bits;
 wherein the bank of programmable registers includes at least 2 N −1 registers that can be selected as the selected register for programming with a data value;  
 wherein the data entries include up to 2 N-1  data values for programming up to 2 N-1  of the 2 N −1 registers using the entries that include the index value,  
 whereby up to 2 N-1  registers in a bank of 2 N −1 registers can be programmed with one index value.  
 
     
     
       5. The graphics engine of  claim 4  wherein the entries stored in the command FIFO include a plurality of entry groups, each entry group containing up to 2 N-1  data entries in the plurality of data entries and one index entry,
 wherein each entry group can program up to 2 N-1  selected registers using 2 N-1 +2 entries in the command FIFO.  
 
     
     
       6. The graphics engine of  claim 5  wherein when at least one of the multi-bit mapping fields contains a disabling value, fewer than 2 N-1  selected registers the bank of programmable registers are written with the plurality of data entries,
 whereby the disabling value in a multi-bit mapping field reduces a number of register programmed.  
 
     
     
       7. The graphics engine of  claim 6  wherein the multi-bit mapping field contains all ones to indicate the disabling value. 
     
     
       8. The graphics engine of  claim 7  further comprising:
 compare logic that compares the multi-bit mapping field to the disabling value and disables writing the data value to the selected register when the multi-bit mapping field contains the disabling value.  
 
     
     
       9. The graphics engine of  claim 6  further comprising:
 a priority encoder coupled to a plurality of compare logic that compares several multi-bit mapping fields in the index value to the disabling value, for determining a count number of multi-bit mapping fields that do not contain the disabling value;  
 wherein the switching bus programs the count number of data values into the count number of selected registers.  
 
     
     
       10. The graphics engine of  claim 6  further comprising:
 a shifter, coupled to the index register, for shifting the index value to apply a  
 different multi-bit mapping field to the decoder in different cycles,  
 whereby the index value is shifted over the different cycles to decode different multi-bit mapping fields in the index register.  
 
     
     
       11. The graphics engine of  claim 10  wherein the host is a central processing unit CPU and the graphics engine is a bit-block-transfer BitBlt engine and the command FIFO is a memory between the host and the BitBlt engine. 
     
     
       12. A method for programming registers comprising:
 sending an address value used to address a first entry in a command FIFO;  
 writing an index value to the first entry in the command FIFO;  
 writing a first data value to a second entry in the command FIFO;  
 writing a second data value to a third entry in the command FIFO;  
 reading the first entry from the command FIFO;  
 reading the index value from the first entry in the command FIFO and writing the index value to an index register;  
 selecting and decoding a first mapping field in the index register, the first mapping field having multiple bits that encode a first register offset that identifies a first selected register in bank of programmable registers;  
 transferring the first data value in the second entry from the command FIFO to the first selected register to write the first selected register with the first data value;  
 selecting and decoding a second mapping field in the index register, the second mapping field having multiple bits that encode a second register offset that identifies a second selected register in bank of programmable registers;  
 transferring the second data value in the third entry from the command FIFO to the second selected register to write the second selected register with the second data value.  
 
     
     
       13. The method of  claim 12  further comprising:
 comparing a third mapping field in the index register to a predetermined disable value;  
 when the third mapping field matches the predetermined disable value, programming a different bank of programmable registers by reading a different first entry from the command FIFO.  
 
     
     
       14. The method of  claim 12  further comprising:
 writing a third data value to a fourth entry in the command FIFO;  
 writing a fourth data value to a fifth entry in the command FIFO;  
 selecting and decoding a third mapping field in the index register, the third mapping field having multiple bits that encode a third register offset that identifies a third selected register in bank of programmable registers;  
 transferring the third data value in the fourth entry from the command FIFO to the third selected register to write the third selected register with the third data value;  
 selecting and decoding a fourth mapping field in the index register, the fourth mapping field having multiple bits that encode a fourth register offset that identifies a fourth selected register in bank of programmable registers; and transferring the fourth data value in the fifth entry from the command FIFO to the fourth selected register to write the fourth selected register with the fourth data value,  
 whereby at least four selected registers are programmed using one index value.  
 
     
     
       15. A programmable controller comprising:
 memory means for storing a plurality of entries from a host, the entries including groups of entries that include a plurality of data entries;  
 wherein each group of entries has multiple data entries;  
 index register means for storing a mapping index that is a data entry in the current group of entries;  
 select means, coupled to the index register means, for selecting a current mapping field from a plurality of mapping fields in the mapping index;  
 decode means, coupled to the select means, for decoding multiple bits in the current mapping field to identify a current register for programming;  
 data transfer means, responsive to the decode means, for transferring one of the plurality of data entries from the current group of entries to the current register to program the current register; and  
 sequencing means for instructing the select means to select another mapping field from the plurality of mapping fields in the mapping index as the current mapping field, the decode means decoding the multiple bits in the current mapping field to identify another current register, the data transfer means transferring another one of the plurality of data entries from the current group of entries to the another current register to program the another current register,  
 whereby multiple registers are programmed from data entries in the current group of entries.  
 
     
     
       16. The programmable controller of  claim 15  further comprising an address match means for causing the decode means to identify current registers from a different bank of programmable registers when an address corresponds to a different bank of programmable registers, wherein the address is an address of the command FIFO or an address field in an index entry in the command FIFO that contains the mapping index. 
     
     
       17. The programmable controller of  claim 15  wherein the mapping index contains a plurality of at least eight mapping fields, wherein the select means can select up to eight different registers as the current register,
 whereby up to eight registers are programmed from the current group of entries.  
 
     
     
       18. The programmable controller of  claim 17  wherein registers are programmed in a sequential or in a non-sequential order wherein registers can be skipped over during programming by a group of entries. 
     
     
       19. The programmable controller of  claim 17  wherein the registers can be programmed in any order. 
     
     
       20. The programmable controller of  claim 17  wherein the memory means comprises a command FIFO for storing graphics data and commands to the programmable controller. 
     
     
       21. An apparatus configured to perform a burst transfer of data values to a bank of programmable registers, the apparatus comprising:
   a first - in - first - out  ( FIFO )  storage unit including an index value storage location and a plurality of data value storage locations, wherein the index value storage location includes a plurality of storage fields, wherein each of said plurality of storage fields is associated with one of the plurality of data value storage locations, wherein each of the storage fields is configured to store a multi - bit destination value indicative of one of the programmable registers within the bank of programmable registers; and        a control unit configured to route data values stored in each of the plurality of data value storage locations from the FIFO storage unit to a respective one of the plurality of programmable registers according to the multi - bit destination value stored in the associated storage field of the index value storage location;      
         wherein, for a given burst transfer to be performed by the apparatus, the index value storage location is configured to receive a plurality of multi - bit destination values to be stored in respective ones of the plurality of storage fields, wherein the apparatus is configured to receive multi - bit destination values only for those programmable registers within the bank of programmable registers that are to be written by the given burst transfer, and wherein the apparatus is configured to perform the given burst transfer by transferring data values only to those programmable registers indicated by the received plurality of multi - bit destination values.   
     
     
       22. The apparatus as recited in  claim 21 , wherein the control unit includes a selector configured to determine an order in which data values stored in the plurality of data value storage locations are routed to their respective programmable registers within the bank of programmable registers. 
     
     
       23. The apparatus as recited in  claim 22 , wherein the control unit includes a counter configured to store a count value indicative of a number of data values stored in the plurality of data value storage locations to be routed to the bank of programmable registers by the control unit. 
     
     
       24. The apparatus as recited in  claim 21 , wherein the control unit includes a decoder configured to decode encoded values stored in the plurality of storage fields in order to route data values from the plurality of data value storage locations to the bank of programmable registers. 
     
     
       25. The apparatus as recited in  claim 21 , wherein the control unit includes a bus switch configured to route data values stored in plurality of data value storage locations to the bank of programmable registers. 
     
     
       26. The apparatus as recited in  claim 21 , wherein the control unit is further configured to select and decode multi- bit destination values stored in each of the plurality of storage fields in order to generate control information for routing data values from the bank of programmable registers to the FIFO storage unit.   
     
     
       27. The apparatus as recited in  claim 26 , wherein the control unit is further configured to route one or more data values from one or more of the registers in the bank of programmable registers to the FIFO storage unit based upon multi- bit destination values stored in a second index value storage location.   
     
     
       28. The apparatus as recited in  claim 21 , wherein each of the plurality of storage fields comprises N bits, and wherein the bank of programmable registers includes up to  2   N   − 1  registers, wherein N is greater than or equal to  2 .   
     
     
       29. The apparatus as recited in  claim 21 , wherein the apparatus is configured to store first and second data values in first and second ones of the plurality of data value storage locations, respectively; and
   wherein, as part of the burst transfer, the apparatus is configured to route the first and second data values to non - consecutive ones of the bank of programmable registers.     
     
     
       30. The apparatus of  claim 21 , wherein, for a burst transfer that is to program a number of programmable registers that is less than the number of the plurality of storage fields, the apparatus is configured such that those storage fields that are not to be utilized during the burst transfer include a value that indicates that the storage field is not indicative of any of the programmable registers within the bank of programmable registers. 
     
     
       31. A method, comprising:
   storing, by a storage device, a plurality of data values to be written to storage locations within a plurality of storage locations by a transfer operation;        storing, by the storage device, an index value for the transfer operation, wherein storing the index value includes storing a first plurality of multi - bit destination location values, wherein each of the first plurality of multi - bit destination location values is associated with one of the plurality of data values, and wherein each of the stored multi - bit destination location values indicates one of the plurality of storage locations, and wherein the stored index value includes multi - bit destination location values only for those storage locations within the plurality of storage locations that are to be written by the transfer operation;        performing the transfer operation by routing each of the plurality of data values from the storage device to one of the plurality of storage locations based upon the associated multi - bit destination location value in the stored index value.     
     
     
       32. The method as recited in  claim 31 , further comprising determining an order in which the plurality of data values are routed to their respective storage locations. 
     
     
       33. The method as recited in  claim 31 , wherein the storage device is a FIFO, and wherein the plurality of storage locations are graphics registers. 
     
     
       34. The method as recited in  claim 31 , further comprising:
   storing, by the storage device, a second index value including a second plurality of multi - bit destination location values; and        selecting and decoding, by the storage device, each of the second plurality of multi - bit destination location values in order to determine one or more data values to be routed from the plurality of storage locations to the storage device, wherein destination location values in the second plurality of multi - bit destination location values are indicative of the storage locations storing data values to be routed to the storage device.     
     
     
       35. The method as recited in  claim 31 , wherein each of the plurality of multi- bit destination location values comprises N bits, and wherein the plurality of destination storage locations comprises up to  2     N   − 1  registers.   
     
     
       36. The method as recited in  claim 31 , wherein performing the transfer operation includes routing data values associated with consecutively stored multi- bit destination location values to non - consecutive ones of the plurality of storage locations.   
     
     
       37. The method of  claim 31 , wherein each of the first plurality of multi- bit destination location values is stored in a respective field of the index value, and wherein performing the transfer operation further includes determining that the stored index value includes a field having a predetermined value that is not indicative of any of the plurality of storage locations, wherein fields in the index value having the predetermined value are not used in completing the transfer operation.   
     
     
       38. An apparatus configured to perform a transfer operation, the apparatus comprising:
   a first - in - first - out  ( FIFO )  storage unit including an index register and a plurality of data storage locations, wherein the index register includes a plurality of fields, each of which is associated with one of the plurality of data storage locations, wherein each of the fields is configured to store a multi - bit destination value indicative of one of a plurality of destination storage locations accessible to the FIFO storage unit, wherein, for a given transfer operation, the FIFO storage unit is configured to receive multi - bit destination values for those data storage locations to be written by the given transfer operation, but not other data storage locations; and        means for routing data values stored in the plurality of data storage locations from the FIFO storage unit to respective ones of the plurality of destination storage locations indicated by the multi - bit destination values stored in the associated fields of the index register.     
     
     
       39. The apparatus as recited in  claim 38 , wherein the means for routing is configured to route data values associated with consecutive fields in the index register to non- consecutive ones of the plurality of destination storage locations.   
     
     
       40. A system comprising:
   a processor;        a first - in - first - out  ( FIFO )  storage unit coupled to the processor and including an index register and a plurality of data storage locations, wherein the index register includes a plurality of fields, wherein each of the plurality of fields is associated with one of the plurality of data storage locations, and wherein each of the fields is configured to store a multi - bit destination value indicative of one of a plurality of destination storage locations; and        a controller coupled to the processor, the FIFO storage unit, and the plurality of destination storage locations;        wherein the controller is configured to perform a transfer operation by routing data values stored in the plurality of data storage locations to respective ones of the plurality of destination storage locations according to the multi - bit destination values stored in the associated fields of the index register;        wherein the apparatus is configured to perform the transfer operation by storing multi - bit destination values in the index register for those ones of the plurality of destination storage locations to be written by the transfer operation, but not other ones of the plurality of destination storage locations.     
     
     
       41. The system as recited in  claim 40 , wherein, for a given transfer operation, the controller is configured to route data values associated with consecutive ones of the plurality of fields in the index register to non- consecutive ones of the plurality of destination storage locations.   
     
     
       42. The system of  claim 40 , wherein the apparatus is configured to perform the transfer operation by storing a predetermined value in one or more fields of the index register, wherein the predetermined value indicates that the one or more fields are not to be used to indicate destination storage locations that are to be written during the transfer operation. 
     
     
       43. An apparatus comprising:
   a first - in - first - out  ( FIFO )  storage unit including an index location and a plurality of data locations, wherein said index location is configured to store an index value having two or more fields, each of which corresponds to a predetermined one of said plurality of data locations, and wherein each of said two or more fields is configured to store a multi - bit storage location value specifying one of a plurality of storage locations external to and accessible by said FIFO;        a control unit configured to perform a transfer operation by routing data from the plurality of storage locations to the plurality of data locations, wherein said control unit is configured, for each of said two or more fields storing a multi - bit storage location value, to route data from the storage location specified by the multi - bit storage location value in the field to the predetermined data location corresponding to the field, wherein the apparatus is configured to implement the transfer operation by including multi - bit storage location values in the index value for those ones of the plurality of storage locations to be transferred as part of the transfer operation, but not other ones of the plurality of storage locations.     
     
     
       44. The apparatus as recited in  claim 43 , wherein, for a given transfer operation, the control unit is configured to route data stored in non- consecutive ones of the plurality of storage locations to ones of the plurality of data locations corresponding to consecutive fields in the index value.