USRE41477EExpiredUtility

Semiconductor device with a reduced mask count buried layer

Individually held — no corporate assignee on recordPriority: Feb 25, 2002Filed: Oct 5, 2004Granted: Aug 10, 2010
Est. expiryFeb 25, 2022(expired)· nominal 20-yr term from priority
Inventors:James D. Beasom
H10W 10/181H10P 90/1906H10W 15/01H10W 15/00H10D 84/673H10D 62/137H10D 10/061H10D 10/60H10D 10/051H10D 10/421
42
PatentIndex Score
0
Cited by
21
References
19
Claims

Abstract

An N type buried layer is formed, in one embodiment, by a non selective implant on the surface of a wafer and later diffusion. Subsequently, the wafer is masked and a selective P type buried layer is formed by implant and diffusion. The coefficient of diffusion of the P type buried layer dopant is greater than the N type buried layer dopant so that connections can be made to the P type buried layer by P wells which have a lower dopant concentration than the N buried layer.

Claims

exact text as granted — not AI-modified
1. A semiconductor device comprising:
 a) an oxide layer;  
 b) a non selective N type buried layer of an N type dopant with a first coefficient of diffusion covering the oxide layer;  
 c) a selective P type buried layer of a P type dopant with a coefficient of diffusion greater than said first coefficient of diffusion located over selective regions of the oxide layer; and  
 d) an N type layer extending over said non selective N type buried layer and said selective P type buried layer, the N type layer having a doping concentration less than the doping concentration of the non selective N type buried layer.  
 
     
     
       2. The semiconductor device set forth in  claim 1  wherein said P type buried layer over compensates completely through said N type buried layer in places where said P type buried layer is formed. 
     
     
       3. The semiconductor device set forth in  claim 1  wherein said P type buried layer does not over compensate completely through the thickness of said N type buried layer. 
     
     
       4. The semiconductor device set forth in  claim 1  wherein a majority dopant in said N type buried layer is one of arsenic or antimony and a majority dopant in said P type buried layer is boron. 
     
     
       5. The semiconductor device set forth in  claim 1  wherein a maximum concentration of an N type majority dopant of said N type buried layer is less than a maximum concentration of a P type majority dopant of said P type buried layer. 
     
     
       6. The semiconductor device set forth in  claim 1  further including:
 a P well extending from said P type buried layer through said N type layer.  
 
     
     
       7. The semiconductor device set forth in  claim 6  wherein an N type majority dopant in said N type buried layer has a maximum concentration greater than the maximum concentration of a P type majority dopant in said P well. 
     
     
       8. A semiconductor device comprising:
 a) an oxide layer;  
 b) an N type buried layer located over the oxide layer;  
 c) a P type buried layer;  
 d) wherein said N type buried layer is non selective and is located over selective regions of the oxide layer;  
 e) wherein said N type buried layer comprises a majority N type dopant having a first coefficient of diffusion;  
 f) wherein said P type buried layer is selective;  
 g) wherein said P type buried layer comprises a majority P type dopant having a coefficient of diffusion greater than said first coefficient of diffusion; and  
 h) an N type layer extending over said non selective N type buried layer and said selective P type buried layer, the N type layer having a doping concentration less than the doping concentration of the non selective N type buried layer.  
 
     
     
       9. The semiconductor device set forth in  claim 8  wherein said P type buried layer over compensates completely through said N type buried layer is places where said P type buried layer is formed. 
     
     
       10. The semiconductor device set forth in  claim 8  wherein said P type buried layer does not over compensate completely through the thickness of said N type buried layer. 
     
     
       11. The semiconductor device set forth in  claim 8  wherein a majority dopant in said N type buried layer is one of arsenic or antimony and a majority dopant in said P type buried layer is boron. 
     
     
       12. The semiconductor device set forth in  claim 8  wherein a maximum concentration of an N type majority dopant of said N type buried layer is less than a maximum concentration of a P type majority dopant of said P type buried layer. 
     
     
       13. The semiconductor device set forth in  claim 8  further including:
 a P well extending from said P type buried layer through said N type layer.  
 
     
     
       14. The semiconductor device set forth in  claim 13  wherein an N type majority dopant in said N type buried layer has a maximum concentration greater than a maximum P type majority dopant concentration in a P well extending from said P type buried layer through an N type layer. 
     
     
       15. A semiconductor device comprising:
   a non selective N type buried layer extending over a first layer;        at least one selective P type buried layer having its entire lateral extent formed in a selected portion of the N type buried layer;        a semiconductor layer extending over the N and P type buried layers, the semiconductor layer having a doping concentration lower than the N type buried layer and is totally separated from the first layer by the non selective N type buried layer and the P type buried layer;        the P type buried layer extending from the N type buried layer into the semiconductor layer; and        a P well extending from the P type buried layer through the semiconductor layer.     
     
     
       16. The semiconductor device set forth in  claim 15  in which the semiconductor layer is N type. 
     
     
       17. The semiconductor device set forth in  claim 15 , wherein the first layer is an insulator. 
     
     
       18. The semiconductor device set forth in  claim 15 , wherein the first layer is a semiconductor substrate. 
     
     
       19. The semiconductor device set forth in  claim 15 , wherein non selective N type buried layer covers the total surface of the first layer.

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