Apparatus for capturing image

Abstract

Apparatus for acquiring an image utilizing serial transmission between the analog-to-digital converting means and the processing means (ASIC) is disclosed herein. The image acquiring system according to the preferred embodiment of the present invention includes the following devices. The image sensor converts an image to an electrical signal responding to a trigger signal. An amplifier amplifies the power of the electrical signal mentioned above, and the amplified electrical signal is of the analog format. The A/D converting device converts the amplified electrical signal from the analog format to the digital format responding to a reference voltage, wherein the A/D converting device outputs the digitized electrical signal in series. The processing device stores the digitized electrical signal in a memory, wherein the trigger signal is generated by the processing device responding to the digitized electrical signal. The reference voltage mentioned above is generated corresponding to a reference digit, wherein the reference digit is generated responding to the digitized electrical signal, the digitized electrical signal being transmitted to the processing means in series.

1. An Apparatus  apparatus for acquiring an image, said apparatus comprising:
 an image sensor for converting the image to an electrical signal responding to a trigger signal;  
 an amplifier for amplifying power of said electrical signal, said amplified electrical signal being of analog format;  
 analog-to-digital converting means for converting said amplified electrical signal from said analog format to digital format responding to a reference voltage, wherein said analog-to-digital converting means outputs said digitized electrical signal in series; and  
 processing means for storing said digitized electrical signal in a memory, said trigger signal being generated by said processing means responding to said digitized electrical signal, said reference voltage being generated corresponding to a reference digit, wherein said reference digit is generated responding to said digitized electrical signal, said digitized electrical signal being transmitted to said processing means in series, wherein said processing means comprises: 
 a serial-in parallel-out register for arranging said digitized electrical signal transmitted by said analog-to-digital converting means in parallel transmission responding to an analog-to-digital clock pulse and a clock pulse, wherein said serial-in parallel-out register comprises: 
 first serial connected delay flip flops for arranging said digitized electrical signal transmitted by said analog-to-digital converting means in parallel transmission responding to said clock pulse; and  
 second serial connected delay flip flops for arranging an output signal from said first serial connected delay flip flops in parallel transmission responding to said analog-to-digital clock pulse; and  
 
 a processor for storing said digitized electrical signal in said memory, wherein said processor generates said analog-to-digital clock pulse and said clock pulse.  
 
 
     
     
       2. The apparatus as  of  claim 1 , wherein said image acquiring apparatus further comprising  comprises:
 sensor driving means for driving said image sensor responding to said trigger signal; and  
 digital-to-analog converting means for generating said reference voltage according to said reference digit.  
 
     
     
       3. The apparatus as  of  claim 1 , wherein said analog-to-digital converting means comprising  comprises:
 an analog-to-digital converter for converting said amplified electrical from said analog format to said digital format by comparing said amplified electrical signal with said reference voltage, wherein said analog-to-digital converter outputs signal in parallel;  
 a parallel-in serial-out register for serially transmitting parallel output of said analog-to-digital converter to said processing means responding to a clock pulse; and  
 controlling means for arranging said digitized electrical signal generated by said analog-to-digital converter in parallel transmission responding to an analog-to-digital clock pulse, said clock pulse and said analog-to-digital clock pulse being generated by said processing means.  
 
     
     
       4. The apparatus as  of  claim 3 , wherein said parallel-in serial-out register comprises:
 a shift register for registering said parallel transmitted digitized electrical signal, said shift register being controlled by said analog-to-digital clock pulse; and  
 a multiplexer for arranging said parallel transmitted digitized electrical signal registered in said shift register in serial transmission responding to output of a  serial connected toggle flip flops, said serial connected toggle flip flops being controlled by said analog-to-digital clock pulse and said clock pulse.  
 
     
     
       5. Apparatus  An apparatus for acquiring an image, said apparatus comprising:
 an image sensor for converting an image to an electrical signal responding to a trigger signal;  
 an amplifier for amplifying power of said electrical signal, said amplified electrical signal being of analog format;  
 analog-to-digital converting means for converting said amplified electrical signal from said analog format to digital format responding to a reference voltage, wherein said analog-to-digital converting means outputs said digitized electrical signal in series, wherein said analog-to-digital converting means comprising  comprises: 
 an analog-to-digital converter for converting said amplified electrical signal from said analog format to said digital format by comparing said amplified electrical signal with said reference voltage, wherein said analog-to-digital converter outputs the digital delectgated  electrical signal in parallel;  
 a parallel-in serial-out register for serially transmitting parallel output of said analog-to-digital converter to said processing means responding to a clock pulse; and  
 controlling means for arranging said digitized electrical signal generated by said analog-to-digital converter in parallel transmission responding to an analog-to-digital clock pulse, said clock pulse and said analog-to-digital clock pulse being generated by said processing means; and  
 
 processing means for storing said digitized electrical signal in a memory, said trigger signal being generated by said processing means responding to said digitized electrical signal, said reference voltage being generated corresponding to a reference digit, wherein said reference digit is generated responding to said digitized electrical signal, said digitized electrical signal being transmitted to said processing means in series, wherein said processing means comprising  comprises: 
 a serial-in parallel-out register for arranging said digitized electrical signal transmitted by said analog-to-digital converting means in parallel transmission responding to said analog-to-digital clock pulse and said clock pulse, wherein said serial-in parallel-out register comprises: 
 first serial connected delay flip flops for arranging said digitized electrical signal transmitted by said analog-to-digital converting means in parallel transmission responding to said clock pulse; and  
 second serial connected delay flip flops for arranging output signal from said first serial connected delay flip flops in parallel transmission responding to said analog-to-digital clock pulse; and  
 
 a processor for storing said digitized electrical signal in said memory, wherein said processor generates said analog-to-digital clock pulse and said clock pulse.  
 
 
     
     
       6. The apparatus as  of  claim 5 , wherein said image acquiring apparatus further comprising  comprises:
 sensor driving means for driving said image sensor responding to said trigger signal; and  
 digital-to-analog converting means for generating said reference voltage according to said reference digit.  
 
     
     
       7. The apparatus as  of  claim 5 , wherein said parallel-in serial-out register comprises:
 a shift register for registering said parallel transmitted digitized electrical signal, said shift register being controlled by said analog-to-digital clock pulse; and  
 a multiplexer for arranging said parallel transmitted digitized electrical signal registered in said shift register in serial transmission responding to output of a  serial connected toggle flip flops, said serial connected toggle flip flops being controlled by said analog-to-digital clock pulse and said clock pulse.  
 
     
     
       8. Apparatus  An apparatus for acquiring image, said apparatus comprising:
 an image sensor for converting an image to an electrical signal responding to a trigger signal;  
 an amplifier for amplifying power of said electrical signal, said amplified electrical signal being of analog format;  
 analog-to-digital converting means for converting said amplified electrical signal from said analog format to digital format responding to a reference voltage, wherein said analog-to-digital converting means output said digitized electrical signal in series, wherein said analog-to-digital converting means comprising  comprises: 
 an analog-to-digital converter for converting said amplified electrical from said analog format to said digital format by comparing said amplified electrical signal with said reference voltage, wherein said analog-to-digital converter outputs signal in parallel;  
 controlling means for arranging said digitized electrical signal generated by said analog-to-digital converter in parallel transmission responding to an analog-to-digital clock pulse; and  
 a parallel-in serial-out register for serially transmitting parallel output of said analog-to-digital converter to said processing means responding to a clock pulse, said clock pulse and said analog-to-digital clock pulse being generated by said processing means, wherein said parallel-in serial-out register comprises: 
 a shift register for registering said parallel transmitted digitized electrical signal, said shift register being controlled by said analog-to-digital clock pulse; and  
 a multiplexer for arranging said parallel transmitted digitized electrical signal registered in said shift register in serial transmission responding to output of a serial connected toggle flip flops, said serial connected toggle flip flops being controlled by said analog-to-digital clock pulse and said clock pulse; and  
 
 
 processing means for storing said digitized electrical signal in a memory, said trigger signal being generated by said processing means responding to said digitized electrical signal, said reference voltage being generated corresponding to a reference digit, wherein said reference digit is generated responding to said digitized electrical signal, said digitized electrical signal being transmitted to said processing means in series, wherein said processing means comprising  comprises: 
 a processor for storing said digitized electrical signal in said memory, wherein said processor generates said analog-to-digital clock pulse and said clock pulse; and  
 a serial-in parallel-out register for arranging said digitized electrical signal transmitted by said analog-to-digital converting means in parallel transmission responding to said analog-to-digital clock pulse and said clock pulse, wherein said serial-in parallel-out register comprises: 
 first serial connected delay flip flops for arranging said digitized electrical signal transmitted by said analog-to-digital converting means in parallel transmission responding to said clock pulse; and  
 second serial connected delay flip flops for arranging output signal from said first serial connected delay flip flops in parallel transmission responding to said analog-to-digital clock pulse.  
 
 
 
     
     
       9. The apparatus as  of  claim 8 , wherein said image acquiring apparatus further comprising  comprises:
 sensor driving means for driving said image sensor responding to said trigger signal; and  
 digital-to-analog converting means for generating said reference voltage according to said reference digit.  
 
     
     
       10. An apparatus comprising:
   an image sensor configured to convert an image to an electrical signal;        an analog - to - digital converter configured to convert the electrical signal from an analog format to a digital format as a digitized electrical signal;        a serial - in parallel - out register configured to receive the digitized electrical signal from said analog - to - digital converter as a series signal, and configured to arrange said digitized electrical signal transmitted by said analog - to - digital converter in parallel transmission responsive to an analog - to - digital clock pulse and a clock pulse, wherein said serial - in parallel - out register comprises:      first serial connected delay flip flops configured to arrange said digitized electrical signal transmitted by said analog - to - digital converter in parallel transmission responsive to the clock pulse;        second serial connected delay flip flops configured to arrange an output signal from said first serial connected delay flip flops in parallel transmission responsive to the analog - to - digital clock pulse; and          a processor configured to store the digitized electrical signal in a memory, said processor configured to generate at least one of the analog - to - digital clock pulse or the clock pulse, or combinations thereof.     
     
     
       11. The apparatus of  claim 10 , further comprising:
   a digital - to - analog converter coupled to at least one of said analog - to - digital converter, said processor, or combinations thereof.     
     
     
       12. The apparatus of  claim 10 , further comprising:
   a parallel - in serial - out register configured to serially transmit a parallel output of said analog - to - digital converter to said processor via said serial - in parallel - out register.     
     
     
       13. The apparatus of  claim 10 , further comprising:
   a parallel - in serial - out register configured to serially transmit a parallel output of said analog - to - digital converter to said processor via said serial - in parallel - out register, said parallel - in serial - out register comprising:      a shift register configured to register the parallel output of said analog - to - digital converter; and        a multiplexer configured to arrange the parallel output of said analog - to - digital converter registered by said shift register as a serial transmission.       
     
     
       14. The apparatus of  claim 10 , wherein said analog- to - digital converter comprises a parallel output analog - to - digital converter.   
     
     
       15. An apparatus comprising:
   an image sensor configured to convert an image to an electrical signal;        analog - to - digital converter configured to convert the electrical signal from an analog format to a digital format as a digitized electrical signal;        a parallel - in serial - out register configured to serially transmit a parallel output of said analog - to - digital converter as a serial signal;        a serial - in parallel - out register configured to receive the parallel output of said analog - to - digital convert as a series signal from said parallel - in serial - out register, said serial - in parallel - out register comprising:      first serial connected delay flip flops configured to arrange the digitized electrical signal transmitted by said analog - to - digital converter as the series signal in parallel transmission responding to a clock pulse; and        second serial connected delay flip flops configured to arrange an output signal from said first serial connected delay flip flops in parallel transmission responding to an analog - to - digital clock pulse; and          a processor configured to store the digitized electrical signal received from the parallel transmission of said series - in parallel - out register in a memory, said processor configured to convert one or more of the analog - to - digital clock pulse or the clock pulse, or combinations thereof.     
     
     
       16. The apparatus of  claim 15 , further comprising:
   a digital - to - analog converter coupled between said processor and said analog - to - digital converter.     
     
     
       17. The apparatus of  claim 15 , wherein said parallel- in serial - out register comprises:      a shift register configured to register the parallel output of said analog - to - digital converter; and        a multiplexer configured to arrange the parallel output of said analog - to - digital converter registered by said shift register as a serial transmission.     
     
     
       18. The apparatus of  claim 15 , wherein said analog- to - digital converter comprises a parallel output analog - to - digital converter.   
     
     
       19. The apparatus of  claim 10 , further comprising a control circuit configured to control said analog- to - digital converter if a sampling operation with said analog - to - digital converter proceeds.   
     
     
       20. An image acquiring system comprising:
   an image sensor configured to convert an image to an electrical signal;        an amplifier to amplify the electrical signal;        an analog - to - digital converter configured to convert the electrical signal received from said amplifier from an analog format to a digital format as a digitized electrical signal;        a parallel - in serial - out register configured to receive the digitized electrical signal from said analog - to - digital converter and arranging the digitized electrical signal in series;        a serial - in parallel - out register configured to receive the digitized electrical signal in series from said parallel - in, serial - out register, and configured to arrange said digitized electrical signal transmitted by said analog - to - digital converter in parallel transmission responsive to an analog - to - digital clock pulse and a clock pulse, wherein said serial - in parallel - out register comprises:      first serial connected delay flip flops configured to arrange said digitized electrical signal transmitted by said analog - to - digital converter in parallel transmission responsive to the clock pulse; and        second serial connected delay flip flops configured to arrange an output signal from said first serial connected delay flip flops in parallel transmission responsive to the analog - to - digital clock pulse;          a processor configured to generate at least one of the analog - to - digital clock pulse or the clock pulse, or combinations thereof;        a memory configured to store the digitize electrical from said processor;        a digital - to - analog converter configured to provide a reference voltage to said analog - to - digital converter in response to a reference digit provided by said processor; and        a sensor drive circuit configured to drive said image sensor responsive to a trigger signal.     
     
     
       21. The image acquiring system of  claim 20 , wherein said parallel- in serial - out register comprises:      a shift register configured to register the parallel output of said analog - to - digital converter; and        a multiplexer configured to arrange the parallel output of said analog - to - digital converter registered by said shift register as a serial transmission.     
     
     
       22. The image acquiring system of  claim 20 , wherein said analog- to - digital converter comprises a parallel output analog - to - digital converter.   
     
     
       23. The image acquiring system of  claim 20 , further comprising a control circuit configured to control said analog- to - digital converter if a sampling operation with said analog - to - digital converter proceeds.