Frequency control system that stabilizes an output through both a counter and voltage-controlled oscillator via sampling a generated clock into four states

Abstract

A frequency control system includes a voltage-controlled oscillator, a sampling circuit for sampling a clock signal produced by the oscillator for two consecutive transitions of an unstable incoming digital signal, and a frequency comparator for incrementing and decrementing a transition upcounter-downcounter controlling the oscillator. The system tolerates variation of the frequency of the incoming signal about a mean value, which has no effect on a clock signal to be extracted by means of a phase comparator or on the synthesized clock signal supplied by the oscillator if the incoming signal contains a high level of jitter and is supplied by a programmable frequency divider.

1. A frequency control system comprising: 
 voltage-controlled oscillator means for generating a clock signal, ;  
 means for receiving a digital incoming signal with unstable frequency for sampling said clock signal at two pairs of times corresponding to two consecutive transitions of said incoming signal in response to each of predetermined transitions of said incoming signal, said times of one pair being separated by a predetermined time-delay at most equal to half the period of said clock signal, to produce four state signals of said clock signal, ;  
 a frequency comparator for combining said four state signals to form an upcounting signal only in response to the frequency of said clock signal being substantially less than the frequency of said incoming signal and to form a downcounting signal only in response to the frequency of said clock signal being greater than the frequency of said incoming signal, ; and  
 upcounting and downcounting means for respectively upcounting and downcounting predetermined transitions of said incoming signal in response to said upcounting signal and said downcounting signal for applying a control voltage dependent on a content of said upcounting and downcounting means to said oscillator means via a digital-to-analog converter.  
 
     
     
       2. The system claimed in  claim 1  wherein said frequency comparator includes a first EXCLUSIVE-OR gate for receiving two state signals corresponding to sampling times of said clock signal between which are sampling times of said clock signal corresponding to the other two state signals, a second EXCLUSIVE-OR gate for receiving said other two state signals, a first AND gate connected directly to said first EXCLUSIVE-OR gate and via an inverter to said second EXCLUSIVE-OR gate to produce said upcounting signal and a second AND gate connected directly to said second EXCLUSIVE-OR gate and via an inverter to said first EXCLUSIVE-OR gate to produce said downcounting signal. 
     
     
       3. The system claimed in  claim 1  wherein said sampling means include means for detecting said predetermined transitions in said incoming signal for producing a transition signal and another transition signal delayed by said predetermined time-delay, and two pairs of flip-flop for respectively producing said state signals and each having a first flip-flop for receiving said clock signal and a second flip-flop having an input connected to the direct output of said first flip-flop, said transition signal and said delayed transition signal being arranged to be respectively applied to clock inputs of said pairs of flip-flops. 
     
     
       4. The system claimed in  claim 3  wherein said transitions detecting means are digital means and comprises a divide-by-four frequency divider for producing a clock signal at half the frequency of said incoming signal, and means for selecting a transition of said incoming signal and a transition in the complementary signal of said incoming signal when it has been complemented, during one half-period in two of said half-frequency clock signal in order to produce said transition signal and said delayed transition signal, respectively. 
     
     
       5. The system claimed in  claim 3 , further comprising latch means connected to said sampling means for selecting from said clock signal and the complementary signal thereof an outgoing clock signal which is more in phase with said incoming signal when said state signals produced by two flip-flops of said pairs of flip-flops are respectively at first and second states and at second and first states, and a flip-flop for reading said incoming signal as a function of said outgoing clock signal. 
     
     
       6. A system as claimed in  claim 1 , further comprising means connected to said sampling means for comparing the phases of said incoming signal and said clock signal as a function of two of said four state signals in order to select from said clock signal and the complementary signal thereof an outgoing clock signal which is more in phase with said incoming signal and which is used to read said incoming signal. 
     
     
       7. A system as claimed in  claim 1 , further comprising programmable frequency divider means for generating said incoming signal to be applied to said sampling means in the form of an unstable reference clock signal having a mean frequency over a respective number of periods equal to a programmed frequency from a unit clock signal having a stable frequency not less than four times the programmed frequency, the ratio between said programmed frequency and said respective number of periods being constant. 
     
     
       8. The system claimed in  claim 7  wherein said programmable frequency divider means comprises an adder and a buffer register clocked at the frequency of said unit clock signal and for storing a sum at outputs of said adder, and said adder being arranged to add said sum to the respective number associated with said programmed frequency. 
     
     
       9. The system claimed in  claim 8  wherein said frequency divider means comprises a divide-by-two frequency divider for receiving a most significant bit of said sum from said buffer register to generate said reference clock signal. 
     
     
       10. The system claimed in  claim 1  wherein said oscillatory means comprises at least one voltage-controlled oscillator arranged to be controlled by said upcounting and downcounting means via a loop filter, and a frequency divider for dividing the frequency of the signal generated by said oscillator by a fixed ratio in order to generate said clock signal. 
     
     
       11. The system claimed in  claim 1  wherein said frequency comparator satisfies the following logic equations:
   H+=(Q 1 .  Q 4   +  Q 1   .Q 4 )(Q 2 .Q 3 +  Q 2   .  Q 3   )  
   H−=(Q 2 .  Q 3   +  Q 2   .Q 3 )(Q 1 .Q 4 +  Q 1   .  Q 4   )  
 
       Q 1 , Q 2 , Q 3  and Q 4  being said four state signals and  Q 1   ,  Q 2   ,  Q 3    and  Q 4    being complement signals thereof. 
     
     
       12. A frequency control signals  system comprising: 
 a voltage-controlled oscillator for generating a clock signal, ;  
 a sampler for receiving a digital input signal having an unstable frequency and for sampling said clock signal at two pairs of times corresponding to two consecutive transitions of said digital input signal, the sampler in response to  being arranged to derive four state signals of said clock signal in response to predetermined transitions of said digital input signal, said times of one pair being separated by a predetermined time-delay at most equal to half the period of said clock signal, ;  
 a frequency comparator for combining said four state signals to form an upcounting signal only in response to the frequency of said clock signal being substantially less than the frequency of said digital input signal and to form a downcounting signal only in response to the frequency of said clock signal being greater than the frequency of said incoming  digital input signal, ; and  
 a counter for respectively upcounting and downcounting predetermined transitions of said digital input signal in response to said upcounting signal and said downcounting signal, ; and  
 a converter responsive to the counter for deriving a control voltage dependent on the count of said counter, the oscillator being arranged to be responsive to the control voltage.  
 
     
     
       13. A system as claimed in  claim 12 , further comprising a phase comparator connected to said sampler for comparing the phases of said incoming signal and said clock signal as a function of two of said four state signals for selecting from said clock signal and the complementat ry signal thereof an outgoing clock signal which is more in phase with said incoming signal and for reading said incoming signal. 
     
     
       14. A system comprising:
   a frequency comparator;        a sampling circuit configured to receive a clock signal and a digital input signal and to output at least four sample values to the frequency comparator in response to each transition of a plurality of transitions of the digital input signal, wherein each of said sample values is a sample of the clock signal;        a counter configured to change a count value in response to transitions of said plurality of transitions, wherein the frequency comparator is configured to operate on said sample values in order to generate one or more control signals that determine whether the counter increases or decreases the count value in response to a transition of said plurality of transitions;        a voltage - controlled oscillator configured to generate the clock signal with a frequency determined by the count value.     
     
     
       15. The system of  claim 14 , wherein a first pair of said sample values are separated by a time delay equal at most to half a period of said clock signal. 
     
     
       16. The system of  claim 14 , wherein the control signals include an upcounting signal and a downcounting signal, wherein the frequency comparator is configured to ( a )  assert the upcounting signal in response to said sample values indicating that the frequency of said clock signal is substantially less than a frequency associated with said digital input signal and  ( b )  assert the downcounting signal in response to said sample values indicating that the frequency of said clock signal is substantially greater than the frequency associated with said digital input signal.   
     
     
       17. The system of  claim 16 , wherein the counter is configured to increase the count value in response to a transisiton of said plurality of transitions if the upcounting signal is asserted and to decrease the count value in response to the transition if the downcounting signal is asserted. 
     
     
       18. The system of  claim 14  further comprising a converter configured to generate a control voltage in response to the count value, wherein the voltage controlled oscillator is configured to receive the control voltage, wherein the control voltage determines the frequency of the clock signal generated by the voltage controlled oscillator. 
     
     
       19. The system of  claim 14 , wherein said plurality of transitions are rising- edge transitions of the digital input signal.   
     
     
       20. The system of  claim 14 , wherein said plurality of transitions are falling- edge transitions of the digital input signal.   
     
     
       21. The system of  claim 14 , wherein said plurality of transitions include rising- edge transitions and falling - edge transitions of the digital input signal.   
     
     
       22. The system of  claim 14 , wherein two of said at least four sample values are captured from said clock signal in response to a current transition of said plurality of transitions, wherein remaining ones of said at least four sample values were captured from said clock signal in response to one or more previous transitions of said plurality of transitions. 
     
     
       23. The system of  claim 14 , wherein the sampling circuit includes:
   two cascaded pairs of flip - flops configured to output the four sample values, wherein a first flip - flop of each pair is configured to receive the clock signal;        a subcircuit configured to receive the digital input signal and to assert a pulse in response to each transition of said plurality of transitions of the digital input signal;        wherein a first of the two cascaded pairs is clocked by the pulse, wherein a second of the two cascaded pairs is clocked by a delayed version of the pulse.     
     
     
       24. A system comprising:
   a frequency comparator;        a sampling circuit configured to receive a first clock signal and a digital input signal and to output at least four sample values to the frequency comparator in response to each transition of a plurality of transitions of the digital input signal, wherein each of said sample values is a sample of the first clock signal;        a counter configured to change a count value in response to transitions of said plurality of transitions, wherein the frequency comparator is configured to operate on said sample values in order to generate one or more control signals that determine whether the counter increases or decreases the count value in response to a transition of said plurality of transitions;        a voltage - controlled oscillator configured to generate a second clock signal with a frequency determined by the count value, wherein the first clock signal has a frequency dependent on the frequency of the second clock signal.     
     
     
       25. The system of  claim 24  further comprising a frequency divider configured to receive the second clock signal and generate the first clock signal from the second clock signal. 
     
     
       26. The system of  claim 24 , wherein said plurality of transitions are rising- edge transitions of the digital input signal.   
     
     
       27. The system of  claim 24 , wherein said plurality of transitions are falling- edge transitions of the digital input signal.   
     
     
       28. The system of  claim 24 , wherein said plurality of transitions include rising- edge transitions and falling - edge transitions of the digital input signal.   
     
     
       29. The system of  claim 24 , wherein two of said at least four sample values are captured from said first clock signal in response to a current transition of said plurality of transitions, wherein remaining ones of said at least four sample values were captured from said first clock signal in response to one or more previous transitions of said plurality of transitions. 
     
     
       30. The system of  claim 24 , wherein the sampling circuit includes:
   two cascaded pairs of flip - flops configured to output the four sample values, wherein a first flip - flop of each pair is configured to receive the first clock signal;        a subcircuit configured to receive the digital input signal and to assert a first pulse and a second pulse in response to each transition of said plurality of transitions of the digital input signal, wherein the second pulse is delayed relative to the first pulse;        wherein a first of the two cascaded pairs is clocked by the pulse, wherein a second of the two cascaded pairs is clocked by the second pulse.     
     
     
       31. The system of  claim 24  further comprising:
   a programmable frequency divider configured to generate the digital input signal with a programmable frequency, wherein the programmable frequency divider includes an adder, a register and a flip - flop, wherein the adder is configured to receive a programmably - selected integer value at its first input and to receive an output of the register at its second input, wherein the register is configured to receive an output of the adder, wherein the register is configured to receive a clock signal HU at its clock input, wherein a most significant bit of the register output is coupled to a clock input of the flip - flop, wherein an output of the flip - flop is coupled to a data input of the flip - flop.     
     
     
       32. A method comprising:
   receiving a clock signal and a digital input signal;        outputting at least four sample values in response to each transition of a plurality of transitions of the digital input signal, wherein each of said sample values is a sample of the clock signal;        changing a count value in response to transitions of said plurality of transitions;        operating on said at least four sample values outputted in response to each transition of said plurality of transitions in order to generate one or more control signals that determine whether the counter increases or decreases the count value in response to a transition of said plurality of transitions;        generating the clock signal with a frequency determined by the count value.     
     
     
       33. The method of  claim 32 , wherein a first pair of said sample values are separated by a time delay equal at most to half a period of said clock signal. 
     
     
       34. The method of  claim 32 , wherein the control signals include an upcounting signal and a downcounting signal, the method further comprising:
 (a) asserting the upcounting signal in response to said sample values indicating that the frequency of said clock signal is substantially less than a frequency associated with said digital input signal and    (b) asserting the downcounting signal in response to said sample values indicating that the frequency of said clock signal is substantially greater than the frequency associated with said digital input signal.   
     
     
       35. The method of  claim 34 , wherein said changing the count includes:
   increasing the count value in response to a transition of said plurality of transitions if the upcounting signal is asserted, and,        decreasing the count value in response to the transition if the downcounting signal is asserted.     
     
     
       36. The method of  claim 32  further comprising converting the count value to a control voltage, wherein the voltage controlled oscillator is configured to receive the control voltage, wherein the control voltage determines the frequency of the clock signal generated by the voltage controlled oscillator. 
     
     
       37. The method of  claim 32 , wherein said plurality of transitions are rising- edge transitions of the digital input signal.   
     
     
       38. The method of  claim 32 , wherein said plurality of transitions are falling- edge transitions of the digital input signal.   
     
     
       39. The method of  claim 32 , wherein said plurality of transitions include rising- edge transitions and falling - edge transitions of the digital input signal.   
     
     
       40. The method of  claim 32 , wherein two of said at least four sample values are captured from said clock signal in response to a current transition of said plurality of transitions, wherein remaining ones of said at least four sample values were captured from said clock signal in response to one or more previous transitions of said plurality of transitions. 
     
     
       41. A method comprising:
   receiving a first clock signal and a digital input signal; and        outputting at least four sample values in response to each transition of a plurality of transitions of the digital input signal, wherein each of said sample values is a sample of the first clock signal;        changing a count value in response to transitions of said plurality of transitions;        operating on said at least four sample values outputted in response to each transition of said plurality of transitions in order to generate one or more control signals that determine whether the counter increases or decreases the count value in response to a transition of said plurality of transitions;        generating a second clock signal with a frequency determined by the count value, wherein the first clock signal has a frequency dependent on the frequency of the second clock signal.     
     
     
       42. The method of  claim 41  further comprising frequency dividing the second clock signal in order to generate the first clock signal. 
     
     
       43. The method of  claim 41 , wherein said plurality of transitions are rising- edge transitions of the digital input signal.   
     
     
       44. The method of  claim 41 , wherein said plurality of transitions are falling- edge transitions of the digital input signal.   
     
     
       45. The method of  claim 41 , wherein said plurality of transitions include rising- edge transitions and falling - edge transitions of the digital input signal.   
     
     
       46. The method of  claim 41 , wherein two of said at least four sample values are captured from said first clock signal in response to a current transition of said plurality of transitions, wherein remaining ones of said at least four sample values were captured from said first clock signal in response to one or more previous transitions of said plurality of transitions. 
     
     
       47. A telecommunication device comprising:
   a frequency comparator;        a sampling circuit configured to receive a clock signal and a digital input signal and to output at least four sample values to the frequency comparator in response to each transition of a plurality of transitions of the digital input signal, wherein each of said sample values is a sample of the clock signal;        a counter configured to change a count value in response to transitions of said plurality of transitions, wherein the frequency comparator is configured to operate on said sample values in order to generate one or more control signals that determine whether the counter increases or decreases the count value in response to a transition of said plurality of transitions;        a voltage - controlled oscillator configured to generate the clock signal with a frequency determined by the count value.     
     
     
       48. The telecommunication device of  claim 47 , wherein the telecommunication device is a receiver. 
     
     
       49. A telecommunication device comprising:
   a frequency comparator;        a sampling circuit configured to receive a first clock signal and a digital input signal and to output at least four sample values to the frequency comparator in response to each transition of a plurality of transitions of the digital input signal, wherein each of said sample values is a sample of the first clock signal;        a counter configured to change a count value in response to transitions of said plurality of transitions, wherein the frequency comparator is configured to operate on said sample values in order to generate one or more control signals that determine whether the counter increases or decreases the count value in response to a transition of said plurality of transitions;        a voltage - controlled oscillator configured to generate a second clock signal with a frequency determined by the count value, wherein the first clock signal has a frequency dependent on the frequency of the second clock signal.     
     
     
       50. The telecommunication device of  claim 49 , wherein the telecommunication device is a receiver. 
     
     
       51. A system comprising:
   a sampling circuit configured to receive a clock signal and a digital input signal and to output at least four sample values in response to each transition of a plurality of transitions of the digital input signal, wherein each of said sample values is a sample of the clock signal;        a counter configured to change a count value in response to transitions of said plurality of transitions;        a frequency comparator that is distinct from the sampling circuit and is configured to operate on said sample values in order to generate one or more control signals that determine whether the counter increases or decreases the count value in response to a transition of said plurality of transitions;        a voltage - controlled oscillator configured to generate the clock signal with a frequency determined by the count value.     
     
     
       52. A system comprising:
   a sampling circuit configured to receive a first clock signal and a digital input signal and to output at least four sample values in response to each transition of a plurality of transitions of the digital input signal, wherein each of said sample values is a sample of the first clock signal;        a counter configured to change a count value in response to transitions of said plurality of transitions;        a frequency comparator that is distinct from the sampling circuit and is configured to operate on said sample values in order to generate one or more control signals that determine whether the counter increases or decreases the count value in response to a transition of said plurality of transitions;        a voltage - controlled oscillator configured to generate a second clock signal with a frequency determined by the count value, wherein the first clock signal has a frequency dependent on the frequency of the second clock signal.     
     
     
       53. A system comprising:
   a sampling circuit configured to receive a clock signal and a digital input signal and to output at least four sample values in response to each transition of a plurality of transitions of the digital input signal, wherein each of said sample values is a sample of the clock signal;        decision logic configured to receive said at least four outputted sample values from the sampling circuit and to operate on said at least four outputted sample values in order to generate one or more control signals;        a counter configured to change a count value in response to transitions of said plurality of transitions, wherein the one or more control signals determine whether the counter increases, decreases or maintains the count value in response to said transition of said plurality of transitions;        a voltage - controlled oscillator configured to generate the clock signal with a frequency determined by the count value.     
     
     
       54. A system comprising:
   a sampling circuit configured to receive a first clock signal and a digital input signal and to output at least four sample values in response to each transition of a plurality of transitions of the digital input signal, wherein each of said sample values is a sample of the first clock signal;        decision logic configured to receive said at least four outputted sample values from the sampling circuit and to operate on said at least four outputted sample values in order to generate one or more control signals;        a counter configured to change a count value in response to transitions of said plurality of transitions, wherein the one or more control signals that determine whether the counter increases, decreases or maintains the count value in response to said transition of said plurality of transitions;        a voltage - controlled oscillator configured to generate a second clock signal with a frequency determined by the count value, wherein the first clock signal has a frequency dependent on the frequency of the second clock signal.     
     
     
       55. A system comprising:
   a sampling circuit configured to receive a clock signal and a digital input signal and to capture a pair of samples of the clock signal in response to each of a plurality of transitions of the digital input signal, wherein the sampling circuit is configured so that the samples of each pair are separated in time by a fixed delay, wherein the sampling circuit is configured to output a current one and a previous one of said pairs in response to each transition of said plurality of transitions;        decision logic configured to operate on said current pair and said previous pair of samples in order to generate one or more control values;        a counter configured to increase, decrease or maintain a count value based on the one or more control values; and        a voltage - controlled oscillator configured to generate the clock signal with a frequency determined by the count value.     
     
     
       56. A system comprising:
   a sampling circuit configured to receive a first clock signal and a digital input signal and to capture a pair of samples of the first clock signal in response to each of a plurality of transitions of the digital input signal, wherein the sampling circuit is configured so that the samples of each pair are separated in time by a fixed delay, wherein the sampling circuit is configured to output a current one and a previous one of said pairs in response to each transition of said plurality of transitions;        decision logic configured to operate on said current pair and said previous pair of samples in order to generate one or more control values;        a counter configured to increase, decrease or maintain a count value based on the one or more control values; and        a voltage - controlled oscillator configured to generate a second clock signal with a frequency determined by the count value, wherein the first clock signal has a frequency dependent on the frequency of the second clock signal.