Integrated circuit having a reduced spacing between a bus and adjacent circuitry

Abstract

An integrated circuit that reduces spacing between circuitry and a bus. In accordance with this invention, the bus is a strip of conductive material in a layer of the integrated circuit. The layer includes at least one slot that removes conductive material from the bus. The removal of the conductive material in the slot allows the space between circuitry adjacent the bus and the bus to be reduced.

1. An integrated circuit that minimizes spacing between circuitry comprising:
 a first circuit in a first layer of said integrated circuit; and  
 a bus in said first layer of said integrated circuit adjacent said first circuit wherein said bus includes a strip of conductive material with at least one slot defined in said strip of conductive material to remove conductive material from said strip to allow a reduction of spacing between said bus and said first circuit wherein spacing between said bus and an adjacent circuit is determined based upon an amount of said conductive material in said strip of conductive material of said bus.  
 
     
     
       2. The integrated circuit of  claim 1  further comprising:
 a second circuit in said first layer of said integrated circuit adjacent to said bus on a side of said bus opposite said first circuit wherein spacing between said bus and said second circuit is reduced because of said removal of conductive material in said at least one slot.  
 
     
     
       3. The integrated circuit of  claim 1  wherein said bus is a power bus. 
     
     
       4. The integrated circuit of  claim 1  wherein said bus is a signal bus. 
     
     
       5. The integrated circuit of  claim 1  wherein said at least one slot defined in said strip of conductive material comprises a plurality of slots defined in said strip of conductive material. 
     
     
       6. The integrated circuit of  claim 5  wherein said slots are evenly spaced in said strip of conductive material. 
     
     
       7. The integrated circuit of  claim 5  wherein said strip of conductive material comprises:
 a first strip of conductive material in said first layer;  
 a second strips of conductive material in said first layer adjacent and substantially parallel to said first strip wherein said second strip is spaced apart from said first strip; and  
 a first plurality of cross connect strips of conductive material that connect said first strip and said second strip wherein a first plurality of slots are defined between said plurality of cross connect strips.  
 
     
     
       8. The integrated circuit of  claim 7  wherein said first plurality of cross connect strips are substantially perpendicular to said first strip and said second strip. 
     
     
       9. The integrated circuit of  7  wherein said strip of conductive material comprises:
 a third strip of conductive material in said first layer that is adjacent to and substantially parallel to said first strip on an opposite side of said first strip of power material from said second strip wherein said third strip is spaced apart from said first strip;  
 a second plurality of cross connect strips of conductive material the connect said third strip to said first strip wherein a second plurality of slots are defined as spaces between adjacent ones of said second plurality of connect strips.  
 
     
     
       10. The integrated circuit of  claim 9  wherein said second plurality of cross connect strips are substantially perpendicular to said first strip and said third strip. 
     
     
       11. The integrated circuit of  claim 9  wherein said second plurality of cross connect strips are spaced evenly apart from one another. 
     
     
       12. The integrated circuit of  claim 9  wherein said second strip and said third strip are connected to said first strip by said first and second plurality of cross connect strips at common points in a flip-flop and abutting manner. 
     
     
       13. The integrated circuit of  claim 9  further comprising:
 a signal source wherein said signal source is connected to each of said first strip, said second strip, and said third strip.  
 
     
     
       14. The integrated circuit of  claim 7  further comprising:
 a signal source wherein said signal source is connected to each of said first strip and said second strip.  
 
     
     
       15. The integrated circuit of  claim 1  further comprising:
 a signal source in second layer of said integrated circuit; and  
 a connector that connects said signal source to said bus on a portion of conductive material of said strip.  
 
     
     
       16. The integrated circuit of  claim 1  wherein spacing between said bus and an adjacent circuit is determined based upon a density of said conductive material in said bus. 
     
     
       17. A method for providing a design of an integrated circuit that provides minimal spacing between a bus that transmits signal and a circuitry adjacent to said bus, said method comprising:
 placing a bus in a first layer of an integrated circuit;  
 defining at least one slot in said bus to remove excess conductive material from said bus to reduce spacing required between said bus and an adjacent circuit;  
 determining an amount of spacing between said bus and said first circuit based upon an amount of conductive material in said bus; and  
 placing a first circuit in said first layer adjacent to said bus on a first side of said bus wherein said spacing between said bus and said first circuit is reduced in response to removing excess conductive material from said bus with said slot in said bus.  
 
     
     
       18. The method of  claim 17  further comprising:
 determining an amount of spacing between said bus and said first circuit is determined based upon a density of said conductive material in said bus.  
 
     
     
       19. The method of  claim 17  further comprising:
 placing a second circuit in said first layer adjacent to said bus on a second side of said bus opposite of said first side wherein spacing between said bus and said second circuit is reduced in response to removing excess conductive material from said bus with said slot in said bus.  
 
     
     
       20. The method of  claim 19  further comprising:
 determining an amount of spacing between said bus and said second circuit based upon an amount of conductive material in said bus.  
 
     
     
       21. The method of  claim 19  further comprising:
 determining an amount of spacing between said bus and said second circuit is determined based upon a density of said conductive material in said bus.  
 
     
     
       22. The method of  claim 17  wherein said step of defining said at least one slot:
 defining a plurality of slots in said strip of conductive material.  
 
     
     
       23. The method of  claim 22  wherein said step of defining said plurality of slots comprises:
 evenly spacing each of said plurality of slots in said strip of conductive material.  
 
     
     
       24. The method of  claim 22  wherein said step of placing said bus comprises:
 placing a first strip of conductive material in said first layer;  
 placing a second strip of conductive material in said first layer adjacent and substantially parallel to said first strip wherein said second strip is spaced apart from said first strip; and  
 connecting said first strip and said second strip with a first plurality of cross connect strips of conductive material in said first layer wherein a first plurality of slots are defined between said plurality of cross connect strips.  
 
     
     
       25. The method of  claim 24  wherein said step of placing said bus further comprises:
 aligning said plurality of cross connect strips substantially perpendicular to said first strip and said second strip.  
 
     
     
       26. The method of  24  said step of placing said bus further comprises:
 placing a third strip of conductive material in said first layer adjacent and substantially parallel to said first strip on an opposite side of said first strip of power material from said second strip wherein said third strip is spaced apart from said first strip; and  
 connecting said third strip to said first strip with a second plurality of cross connect strips of conductive material wherein a second plurality of slots are defined as spaces between adjacent ones of said second plurality of connect strips.  
 
     
     
       27. The method of  claim 26  wherein said step of connecting said first step and said third strip comprises:
 placing said second plurality of cross connects strips substantially perpendicular to said first strip and said third strip.  
 
     
     
       28. The method of  claim 26  wherein step of connecting said first strip and said third strip further comprises:
 spacing said second plurality of cross connect strips evenly apart from one another.  
 
     
     
       29. The method of  claim 26  further comprising:
 connecting said second strip and said third strip to said first strip by said first and second plurality of cross connect strips at common points in a flip-flop and abutting manner.  
 
     
     
       30. The method of  claim 26  further comprising;
 connecting a signal source to each of said first strip, said second strip, and said third strip.  
 
     
     
       31. The method of  claim 24  further comprising:
 connecting a signal source to each of said first strip, and said second strip.  
 
     
     
       32. The method of  claim 17  further comprising:
 connecting a signal source in second layer of said integrated circuit in a portion of conductive material of said strip.  
 
     
     
       33. The method of  claim 17  further comprising:
 providing said design of said integrated circuit to a manufacturer.  
 
     
     
       34. An integrated circuit comprising:
   a first circuit formed in a first layer of said integrated circuit; and        a bus formed in said first layer of said integrated circuit adjacent said first circuit, said bus including a strip of conductive material with at least one slot formed therein to allow a reduction of spacing between said bus and said first circuit, wherein said spacing between said bus and said first circuit is determined based, at least in part, upon an amount of said conductive material in said strip of conductive material of said bus.     
     
     
       35. The integrated circuit of  claim 34 , and further comprising:
   a second circuit in said first layer of said integrated circuit adjacent to said bus on a side of said bus opposite said first circuit, wherein said at least one slot allows a reduction in spacing between said bus and said second circuit.     
     
     
       36. The integrated circuit of  claim 34 , wherein said bus comprises a power bus. 
     
     
       37. The integrated circuit of  claim 34 , wherein said bus comprises a signal bus. 
     
     
       38. The integrated circuit of  claim 34 , wherein said at least one slot formed in said strip of conductive material comprises a plurality of slots formed in said strip of conductive material. 
     
     
       39. The integrated circuit of  claim 38  wherein said slots are evenly spaced in said strip of conductive material. 
     
     
       40. The integrated circuit of  claim 38 , wherein said strip of conductive material comprises:
   a first strip of conductive material in said first layer;        a second strip of conductive material in said first layer adjacent and substantially parallel to said first strip, said second strip being spaced apart from said first strip; and        a first plurality of cross connect strips of conductive material that connect said first strip and said second strip, wherein a first plurality of slots are formed between said plurality of cross connect strips.     
     
     
       41. The integrated circuit of  claim 40 , wherein said first plurality of cross connect strips are substantially perpendicular to said first strip and said second strip. 
     
     
       42. The integrated circuit of  40 , wherein said strip of conductive material comprises:
   a third strip of conductive material in said first layer that is adjacent to and substantially parallel to said first strip on an opposite side of said first strip of power material from said second strip, said third strip being spaced apart from said first strip;        a second plurality of cross connect strips of conductive material to connect said third strip to said first strip, wherein a second plurality of slots are defined as spaces between adjacent ones of said second plurality of connect strips.     
     
     
       43. The integrated circuit of  claim 42 , wherein said second plurality of cross connect strips are substantially perpendicular to said first strip and said third strip. 
     
     
       44. The integrated circuit of  claim 42 , wherein said second plurality of cross connect strips are spaced substantially evenly apart from one another. 
     
     
       45. The integrated circuit of  claim 42 , wherein said second strip and said third strip are connected to said first strip by said first and second plurality of cross connect strips at common points in a flip- flop and abutting manner.   
     
     
       46. The integrated circuit of  claim 42 , and further comprising:
   a signal source connected to at least one of said first strip, said second strip, and/or said third strip.     
     
     
       47. The integrated circuit of  claim 40 , and further comprising:
   a signal source connected to at least one of said first strip and/or said second strip.     
     
     
       48. The integrated circuit of  claim 34 , and further comprising:
   a signal source in second layer of said integrated circuit; and        a connector to connect said signal source to said bus on a portion of conductive material of said strip.     
     
     
       49. The integrated circuit of  claim 34 , wherein spacing between said bus and an adjacent circuit is determined based, at least in part, upon a density of said conductive material in said bus. 
     
     
       50. A method for providing a design of an integrated circuit, said method comprising:
   defining a bus in a first layer of an integrated circuit;        defining at least one slot in said bus to enable a reduction in spacing between said bus and an adjacent circuit;        determining an amount of spacing between said bus and said adjacent circuit based, at least in part, upon an amount of conductive material in said bus; and        defining a first circuit in said first layer adjacent to said bus on a first side of said bus, wherein said spacing between said bus and said first circuit is reduced in response to removal of conductive material from said bus.     
     
     
       51. The method of  claim 50 , and further comprising:
   determining an amount of spacing between said bus and said first circuit is determined based, at least in part, upon a density of said conductive material in said bus.     
     
     
       52. The method of  claim 50 , and further comprising:
   placing a second circuit in said first layer adjacent to said bus on a second side of said bus opposite of said first side, wherein spacing between said bus and said second circuit is reduced in response to removing excess conductive material from said bus with said slot in said bus.     
     
     
       53. The method of  claim 52 , and further comprising:
   determining an amount of spacing between said bus and said second circuit based, at least in part, upon an amount of conductive material in said bus.     
     
     
       54. The method of  claim 52 , and further comprising:
   determining an amount of spacing between said bus and said second circuit is determined based, at least in part, upon a density of said conductive material in said bus.     
     
     
       55. The method of  claim 50 , wherein said defining said at least one slot further comprises:
   defining a plurality of slots in said strip of conductive material.     
     
     
       56. The method of  claim 55  wherein said defining said plurality of slots further comprises:
   evenly spacing said plurality of slots in said strip of conductive material.     
     
     
       57. The method of  claim 55 , wherein said defining said bus further comprises:
   defining a first strip of conductive material in said first layer;        defining a second strip of conductive material in said first layer adjacent and substantially parallel to said first strip wherein said second strip is spaced apart from said first strip; and        connecting said first strip and said second strip with a first plurality of cross connect strips of conductive material in said first layer wherein a first plurality of slots are defined between said plurality of cross connect strips.     
     
     
       58. The method of  claim 57 , wherein said defining said bus further comprises:
   defining said plurality of cross connect strips to be substantially perpendicular to said first strip and said second strip.     
     
     
       59. The method of  57 , said defining said bus further comprises:
   defining a third strip of conductive material in said first layer adjacent and substantially parallel to said first strip on an opposite side of said first strip of power material from said second strip, said third strip being spaced apart from said first strip; and        defining a second plurality of cross connect strips of conductive material to connect said third strip to said first strip, wherein a second plurality of slots are defined as spaces between adjacent ones of said second plurality of connect strips.     
     
     
       60. The method of  claim 59 , wherein said defining said second plurality of cross connect strips of conductive material further comprises:
   defining said second plurality of cross connect strips to be substantially perpendicular to said first strip and said third strip.     
     
     
       61. The method of  claim 59 , wherein said defining said second plurality of cross connect strips of conductive material further comprises:
   spacing said second plurality of cross connect strips substantially evenly apart from one another.     
     
     
       62. The method of  claim 59 , and further comprising:
   defining connection of said second strip and said third strip to said first strip by said first and second plurality of cross connect strips at common points in a flip - flop and abutting manner.     
     
     
       63. The method of  claim 59 , and further comprising:
   defining connection of a signal Source to at least one of said first strip, said second strip, and/or said third strip.     
     
     
       64. The method of  claim 57 , and further comprising:
   defining connection of a signal source to at least one of said first strip, and/or said second strip.     
     
     
       65. The method of  claim 50 , and further comprising:
   defining connection of a signal source in a second layer of said integrated circuit to a portion of conductive material of said strip.     
     
     
       66. The method of  claim 50 , and further comprising:
   providing said design of said integrated circuit to a manufacturer.