Device and methods for repeatedly updating the function of a LCD monitor

Abstract

A monitor control system capable of reprogramming the function of a LCD monitor. The monitor control system utilizes VGA signal lines for video signal transmission during normal mode of operation and the same VGA signal lines for transmitting erase/record commands and data when the erasable programmable ROM inside the monitor demands reprogramming. Using an isolator circuit in the monitor control system for isolating an erase/record pathway of an erasable programmable ROM from a normal video pathway, data within the erasable programmable ROM can be modified without opening up the monitor casing. Hence, the modification of monitor function is much more convenient.

1. A device for reprogramming the function of a liquid crystal display (LCD) monitor, comprising:
 a set of video graphic adapter (VGA) signal lines for transmitting a plurality of erase/record commands and a plurality of erase/record data;    a signal detector coupled to the VGA signal lines for detecting and re-transmitting the erase/record commands and data;    an activation device coupled to the signal detector, wherein the activation device is normally connected to a video pathway, but as soon as erase/record commands are detected, the activation device is switched to an erase/record pathway so that erase/record commands and data can be re-directed;    a read-only-memory (ROM) erase/record command decoder connected to the activation device via the erase/record pathway, wherein the decoder translates the erase/record commands into a plurality of control signals and translates the erase/record data into a plurality of address signals and a plurality of data signals;    a plurality of signal lines for transferring the control signals, the address signals, and the data signals to an external ROM unit, wherein a content of the ROM unit can be modified according to the control signals, the address signals, and the data signals; and    a mode return device coupled to the ROM erase/record command decoder and the activation device, wherein the reprogramming status of the ROM unit can be determined from the address, data and read/write signals so that the activation device can be triggered to switch over connection from the erase/record pathway to the video pathway as soon as reprogramming is finished.    
     
     
       2. The device of  claim 1 , wherein the erase/record commands and data come from an erase/record device that couples to the VGA signal lines. 
     
     
       3. The device of  claim 2 , wherein the erase/record device is a computer platform that sends the erase/record commands and data in an inter-integrated circuit interface format via a parallel port VGA adapter. 
     
     
       4. The device of  claim 2 , wherein the erase/record device is an inter-integrated circuit interface circuit platform for transmitting erase/record commands and data in an inter-integrated circuit interface format. 
     
     
       5. The device of  claim 1 , wherein the signal detector further includes:
 an inter-integrated circuit multiple address content comparator circuit coupled to the VGA signal lines for comparing with a plurality of consecutive address sequences in the erase/record data such that a set signal is transmitted when there is a match with a pre-set address sequence; and    a monitor-in-system programming control flag unit coupled to the inter-integrated circuit multiple address content comparator circuit for transmitting a start signal after receiving the set signal.    
     
     
       6. The device of  claim 1 , wherein the activation device further includes:
 a monitor-in-system reprogramming initialization circuit for producing a select signal after receiving the start signal; and    an erase/record pathway isolator for switching over connection from the video pathway to the erase/record pathway after receiving the select signal and transmitting the erase/record commands and data via the erase/record pathway.    
     
     
       7. The device of  claim 1 , wherein the ROM erase/record command decoder further includes:
 an inter-integrated interface circuit for receiving and translating the erase/record commands and data; and    an erase/record command decoder for receiving translated erase/record commands and data and outputting address, data and erase/read/write signals.    
     
     
       8. The device of  claim 7 , wherein the erase/record command decoder further includes:
 a hidden ROM for holding a program code for erase/record commands;    a random access memory (RAM) unit for holding erase/record data;    a central processing unit coupled to the hidden ROM, the RAM unit and the inter-integrated interface circuit, wherein the central processing unit receives the erase/record commands and data passing through the inter-integrated circuit interface circuit and then stores the erase/record data in the RAM unit, while the erase/record commands are decoded by referring to the program code in the hidden ROM and then the decoded commands are re-transmitted; and    an erase/record control register coupled to the central processing unit for receiving the decoded erase/record commands and converting the erase/record commands into the interface control signals or erase/read/write signals, and converting the erase/record data stored in the RAM unit into address and data signals.    
     
     
       9. The device of  claim 7 , wherein the erase/record command decoder is a hardware circuit that separates each erase/record command picked up by the inter-integrated circuit into a plurality of states for ease of decoding and converts the erase/record commands and data into erase/read/write, address and data signals. 
     
     
       10. The device of  claim 1 , wherein the mode return device further includes:
 a mode return control register for receiving the address, data and erase/read/write signals and producing a mode return signal as soon as a reprogramming operation is finished; and    a mode return circuit coupled to the mode return control register and the activation device for sending a stop signal to the activation device after receiving the mode return signal so that the activation device switches over connection from the erase/record pathway back to the video pathway.    
     
     
       11. The device of  claim 1 , wherein the external ROM unit comprises a flash ROM unit. 
     
     
       12. The device of  claim 1 , wherein the external ROM unit comprises an erasable programmable ROM unit. 
     
     
       13. A system for reprogramming the function of a liquid crystal display (LCD) monitor, comprising:
 an erase/record device for holding and transmitting a plurality of erase/record commands and a plurality of erase/record data;    a set of video graphic adapter (VGA) signal lines coupled to the erase/record device for transmitting the erase/record commands and data; and    a LCD monitor controller with a monitor-in-system programming function, wherein the LCD monitor controller is coupled to the VGA signal lines so that the erase/record commands of the erase/record device and data are received from the erase/record device via the VGA signal lines, and then a plurality of address signals, a plurality of data signals, and a plurality of control signals are exported for reprogramming a ROM unit, wherein    the ROM unit coupled to the LCD monitor controller via signal lines for transferring the address signals, the data signals and the control signals, so that data stored in the ROM unit can be modified according to the address signals and the control signals, and the data signals coming from the LCD monitor controller.    
     
     
       14. The system of  claim 13 , wherein the erase/record device is a computer platform that sends the erase/record commands and data in an inter-integrated circuit interface format via a parallel port VGA adapter. 
     
     
       15. The system of  claim 13 , wherein the erase/record device is an inter-integrated circuit interface circuit platform for transmitting erase/record commands and data in an inter-integrated circuit interface format. 
     
     
       16. The system of  claim 13 , wherein the LCD monitor controller with monitor-in-system programming function includes:
 a signal detector coupled to the VGA signal lines for detecting and transmitting the erase/record commands and data;    an activation device coupled to the signal detector, wherein the activation device is normally connected to a video pathway, but as soon as erase/record commands is detected, the activation device is switched to an erase/record pathway so that erase/record commands and data can be re-directed;    a ROM erase/record command decoder connected to the activation device via the erase/record pathway, wherein the decoder translates the erase/record commands into a plurality of erase/read/write signals and translates the erase/record data into a plurality of address signals and a plurality of data signals; and    a mode return device coupled to the ROM record command decoder and the activation device, wherein the reprogramming status of a ROM unit can be determined from the address, data and erase/read/write signals so that the activation device can be triggered to switch over connection from the erase/record pathway to the video pathway as soon as reprogramming is finished.    
     
     
       17. The system of  claim 16 , wherein the signal detector further includes:
 an inter-integrated circuit multiple address content comparator circuit coupled to the VGA signal lines for comparing with a plurality of consecutive address sequences in the erase/record data such that a set signal is transmitted when there is a match with a pre-set address sequence; and    a monitor-in-system programming control flag unit coupled to the inter-integrated circuit multiple address content comparator circuit for transmitting a start signal after receiving the set signal.    
     
     
       18. The system of  claim 16 , wherein the activation device further includes:
 a monitor-in-system reprogramming initialization circuit for producing a select signal after receiving the start signal; and    an erase/record pathway isolator for switching over connection from the video pathway to the erase/record pathway after receiving the select signal and transmitting the erase/record commands and data via the erase/record pathway.    
     
     
       19. The system of  claim 16 , wherein the ROM erase/record command decoder further includes:
 an inter-integrated interface circuit for receiving and translating the erase/record commands and data; and    an erase/record command decoder for receiving translated erase/record commands and data and outputting address, data and erase/read/write signals.    
     
     
       20. The system of  claim 19 , wherein the erase/record command decoder further includes:
 a hidden ROM for holding a program code for erase/record commands;    a random access memory (RAM) unit for holding erase/record data;    a central processing unit coupled to the hidden ROM, the RAM unit and the inter-integrated interface circuit, wherein the central processing unit receives the erase/record commands and data passing through the inter-integrated circuit interface circuit and then stores the erase/record data in the RAM unit, while the erase/record commands are decoded by referring to the program code in the hidden ROM after which the decoded commands are re-transmitted; and    an erase/record control register coupled to the central processing unit for receiving the decoded erase/record commands and converting the erase/record commands into the interface control signals or erase/read/write signals, and converting the erase/record data stored in the RAM unit into address and data signals.    
     
     
       21. The system of  claim 19 , wherein the erase/record command decoder is a hardware circuit that separates each erase/record command picked up by the inter-integrated circuit into a plurality of states for ease of decoding and converts the erase/record commands and data into erase/read/write, address and data signals. 
     
     
       22. The system of  claim 16 , wherein the mode return device further includes:
 a mode return control register for receiving the address, data and read/write signals and producing a mode return signal as soon as a reprogramming operation is finished; and    a mode return circuit coupled to the mode return control register and the activation device for sending a stop signal to the activation device after receiving the mode return signal so that the activation device switches connection from the erase/record pathway back to the video pathway.    
     
     
       23. The system of  claim 13 , wherein the ROM unit inside the monitor controller is a flash ROM unit. 
     
     
       24. The system of  claim 13 , wherein the ROM unit comprises an erasable programmable ROM unit. 
     
     
       25. A method for reprogramming the function of a liquid crystal display (LCD) monitor system, comprising the steps of:
 tapping a plurality of signals from a set of video graphic adapter (VGA) signal lines to perform a plurality of consecutive address sequence comparisons with a pre-set address sequence;    triggering a programming mode inside the LCD monitor system when one of the tapped consecutive address sequences matches that of the pre-set address sequence;    reading an erase/record command and deciding what actions to take as soon as the programming mode is activated;    reading in erase/record data and writing the erase/record data into a memory unit when the erase/record command is for a write operation, and then returning to the previous step; and    returning to the very first step when the erase/record command demands a return to a non-programming mode.    
     
     
       26. The method of  claim 25 , wherein reprogramming starts only when the LCD monitor system is not operating in a normal mode. 
     
     
       27. The method of  claim 25 , wherein the LCD monitor system continues to operate in a normal video transmission mode when the tapped consecutive address sequence does not match any pre-set address sequence. 
     
     
       28. A device of a display for updating the function of the display, comprising:
   a set of video signal lines for transmitting a plurality of video signals or a recording signal, wherein the recording signal comprises a recording command and a recorded data;        a signal detector couple to the video signal lines for detecting and re - transmitting the recording command and the recorded data; and        a display controller couple to the signal detector, wherein the display controller is normally connected to a video pathway, but after the signal detector detects the recording signal, the display controller switches to a recording pathway, and the display controller decodes the recording signal and transfers the decoded recording signal to a non - volatile memory through the recording pathway, wherein a content of the non - volatile memory can be modified according to the decoded recording signal.     
     
     
       29. The device of  claim 28 , wherein the video signals come from a video generating device which couples to the video signal lines. 
     
     
       30. The device of  claim 29 , wherein the video generating device comprises a digital versatile disc ( DVD )  player.   
     
     
       31. The device of  claim 29 , wherein the video generating device comprises an antenna and a tuner. 
     
     
       32. The device of  claim 29 , wherein the video generating device comprises a set top box. 
     
     
       33. The device of  claim 29 , wherein the video generating device comprises a computer system. 
     
     
       34. The device of  claim 28 , wherein the recording signal comes from a recording device that couples to the video signal lines. 
     
     
       35. The device of  claim 34 , wherein the recording device is a computer system that sends the recording signal to the video signal lines. 
     
     
       36. The device of  claim 34 , wherein the recording device is a computer platform that sends the recording commands and the recorded data in an inter- integrated circuit interface format via a video port.   
     
     
       37. The device of  claim 34 , wherein the recording device is an inter- integrated circuit interface circuit platform for transmitting the recording command and recorded data in an inter - integrated circuit interface format.   
     
     
       38. The device of  claim 28 , wherein the signal detector further includes:
   an address content comparator circuit coupled to the video signal lines for comparing with an address in the recorded data such that a set signal is transmitted when there is a match with a pre - set address; and        a programming control flag unit coupled to the address content comparator circuit for transmitting a start signal after receiving the set signal.     
     
     
       39. The device of  claim 38 , wherein the display controller further includes:
   a reprogramming initialization circuit for producing a select signal after receiving the start signal; and        a recording pathway isolator for switching over connection from the video pathway to the recording pathway after receiving the select signal and transmitting the recording command and the recorded data via the recording pathway.     
     
     
       40. The device of  claim 28 , wherein the display controller further includes:
   an interface circuit for receiving and translating the recording command and the recorded data; and        a command decoder for receiving translated the recording command and the recorded data and outputting erase/read/write and data signals.     
     
     
       41. The device of  claim 40 , wherein the command decoder further includes:
   a ROM with a program code for the recording command;        a random access memory  ( RAM )  unit for holding the recorded data;        a central processing unit coupled to the ROM, the RAM unit and the interface circuit, wherein the central processing unit receives the recording command and the recorded data passing through the interface circuit and then stores the recorded data in the RAM unit, while the recording command is decoded by referring to the program code in the ROM and then the decoded command is re - transmitted; and        a control register coupled to the central processing unit for receiving the decoded recording command and converting the recording command into an interface control signal or erase/read/write signals and converting the recorded data stored in the RAM unit into the data signals.     
     
     
       42. The device of  claim 40 , wherein the command decoder is a hardware circuit that separates the recording command picked up by the interface circuit into a plurality of states for ease of decoding and converts the recording command and the recorded data into erase/read/write and data signals. 
     
     
       43. The device of  claim 28 , wherein the display controller further includes:
   a mode return control register for receiving the decoded recording signal and producing a mode return signal after a reprogramming operation is finished; and        a mode return circuit coupled to the mode return control register for sending a stop signal to the display controller after receiving the mode return signal so that the display controller switches over connection from the recording pathway back to the video pathway.     
     
     
       44. The device of  claim 28 , wherein the video signal lines comprise video graphic adapter ( VGA )  signal lines.   
     
     
       45. The device of  claim 28 , wherein the video signal lines comprise digital visual interface ( DVI )  signal lines.   
     
     
       46. The device of  claim 28 , wherein the video signal lines comprise high definition multimedia interface ( HDMI )  signal lines.   
     
     
       47. The device of  claim 28 , wherein the video signal lines comprise component video lines. 
     
     
       48. The device of  claim 28 , wherein the video signal lines comprise S- video lines.   
     
     
       49. The device of  claim 28 , wherein the non- volatile memory comprises a flash ROM.   
     
     
       50. The device of  claim 28 , wherein the non- volatile memory comprises an electrically erasable programmable read only memory.   
     
     
       51. A method for reprogramming the function of a display system, comprising the steps of:
   tapping a plurality of signals from a set of video signal lines to perform an address comparison with a pre - set address;        triggering a programming mode inside the display system when one of the tapped address matches that of the pre - set address;        reading a recording command and deciding what action to take after the programming mode is activated;        reading in recorded data and writing the recorded data into a memory unit when the recording command is for a write operation, and then returning to the previous step; and        returning to the first step when the recording command demands a return to a non - programming mode.     
     
     
       52. The method of  claim 51 , wherein reprogramming starts only when the display system is not operating in a normal mode. 
     
     
       53. The method of  claim 51 , wherein the display system continues to operate in a normal video transmission mode when the tapped address does not match any pre- set address.   
     
     
       54. A system for reprogramming the function of a display, comprising:
   a recording device for holding and transmitting a recording command and recorded data;        a set of video signal lines coupled to the recording device for transmitting the recording command and the recorded data; and        a display controller with a monitor - in - system programming function, wherein the display controller is coupled to the video signal lines so that the recording command of the recording device and the recorded data are received from the recording device via the video signal lines, and then a plurality of data signals, and a control signal are exported for reprogramming a ROM unit, wherein        the ROM unit coupled to the display controller via signal lines for transferring the data signals and the control signal, so that data stored in the ROM unit can be modified according to the data signals and the control signal, and the data signals coming from the display controller.     
     
     
       55. The system of  claim 54 , wherein the recording device is a computer platform that sends the recording command and the recorded data in an inter- integrated circuit interface format via a video port.   
     
     
       56. The system of  claim 54 , wherein the recording device is an inter- integrated circuit interface circuit platform for transmitting recording command and recorded data in an inter - integrated circuit interface format.   
     
     
       57. The system of  claim 54 , wherein the display controller with monitor- in - system programming function includes:      a signal detector coupled to the video signal lines for detecting and transmitting the recording command and the recorded data;        an activation device coupled to the signal detector, wherein the activation device is normally connected to a video pathway, but when the recording command is detected, the activation device is switched to a recording pathway so that the recording command and the recorded data can be re - directed;        a command decoder connected to the activation device via the recording pathway, wherein the decoder translates the recording command into a plurality of erase/read/write signals and translates the recorded data into a plurality of address signals and a plurality of data signals; and        a mode return device coupled to the command decoder and the activation device, wherein the reprogramming status of a ROM unit can be determined from the address, data and erase/read/write signals so that the activation device can be triggered to switch over connection from the recording pathway to the video pathway after reprogramming is finished.     
     
     
       58. The system of  claim 57 , wherein the signal detector further includes:
   an inter - integrated circuit address content comparator circuit coupled to the video signal lines for comparing with an address in the recorded data such that a set signal is transmitted when there is a match with a pre - set address; and        a monitor - in - system programming control flag unit coupled to the inter - integrated circuit address content comparator circuit for transmitting a start signal after receiving the set signal.     
     
     
       59. The system of  claim 57 , wherein the activation device further includes:
   a monitor - in - system reprogramming initialization circuit for producing a select signal after receiving the start signal; and        an recording pathway isolator for switching over connection from the video pathway to the recording pathway after receiving the select signal and transmitting the recording command and the recorded data via the recording pathway.     
     
     
       60. The system of  claim 57 , wherein the command decoder further includes:
   an inter - integrated circuit interface circuit for receiving and translating the recording command and the recorded data; and        an erase/record command decoder for receiving translated recording command and recorded data and outputting address, data and erase/read/write signals.     
     
     
       61. The system of  claim 60 , wherein the erase/record command decoder further includes:
   a hidden ROM for holding a program code for the recording command;        a random access memory  ( RAM )  unit for holding the recorded data;        a central processing unit coupled to the hidden ROM, the RAM unit and the inter - integrated circuit interface circuit, wherein the central processing unit receives the recording command and the recorded data passing through the inter - integrated circuit interface circuit and then stores the recorded data in the RAM unit, while the recording command is decoded by referring to the program code in the hidden ROM after which the decoded command is re - transmitted; and        a recording control register coupled to the central processing unit for receiving the decoded recording command and converting the recording command into the interface control signals or erase/read/write signals, and converting the recorded data stored in the RAM unit into the address and data signals.     
     
     
       62. The system of  claim 60 , wherein the erase/record command decoder is a hardware circuit that separates the recording command picked up by the inter- integrated circuit interface circuit into a plurality of states for ease of decoding and converts the recording command and the recorded data into erase/read/write, address and data signals.   
     
     
       63. The system of  claim 60 , wherein the mode return device further includes:
   a mode return control register for receiving the address, data and read/write signals and producing a mode return signal after a reprogramming operation is finished; and        a mode return circuit coupled to the mode return control register and the activation device for sending a stop signal to the activation device after receiving the mode return signal so that the activation device switches connection from the recording pathway to the video pathway.     
     
     
       64. The device of  claim 54 , wherein the video signal lines comprise video graphic adapter ( VGA )  signal lines.   
     
     
       65. The device of  claim 54 , wherein the video signal lines comprise digital visual interface ( DVI )  signal lines.   
     
     
       66. The device of  claim 54 , wherein the video signal lines comprise high definition multimedia interface ( HDMI )  signal lines.   
     
     
       67. The device of  claim 54 , wherein the video signal lines comprise component video lines. 
     
     
       68. The device of  claim 54 , wherein the video signal lines comprise S- video lines.   
     
     
       69. The system of  claim 54 , wherein the ROM unit inside the monitor controller is a flash ROM unit. 
     
     
       70. The system of  claim 54 , wherein the ROM unit comprises an erasable programmable ROM unit. 
     
     
       71. A device for reprogramming the function of a display, comprising:
   a set of video signal lines for transmitting a recording signal which comprises a recording command and a recorded data;        a signal detector coupled to the video signal lines for detecting and re - transmitting the recording command and the recorded data;        an activation device coupled to the signal detector, wherein the activation device is normally connected to a video pathway, but after the recording command is detected, the activation device is switched to a recording pathway so that the recording command and the recorded data can be re - directed;        a command decoder connected to the activation device via the recording pathway, wherein the decoder translates the recording command into a control signal and translates the recorded data into a plurality of data signals;        a plurality of signal lines for transferring the control signal and the data signals to an external ROM unit, wherein a content of the ROM unit can be modified according to the control signal and the data signals; and        a mode return device coupled to the command decoder and the activation device, wherein the reprogramming status of the ROM unit can be determined from the recording signal so that the activation device can be triggered to switch over connection from the recording pathway to the video pathway after reprogramming is finished.     
     
     
       72. The device of  claim 71 , wherein the recording command and the recorded data come from a recording device that couples to the video signal lines. 
     
     
       73. The device of  claim 72 , wherein the recording device is a computer platform that sends the recording commands and the recorded data in an inter- integrated circuit interface format via a video port.   
     
     
       74. The device of  claim 72 , wherein the recording device is an inter- integrated circuit interface circuit platform for transmitting the recording command and the recorded data in an inter - integrated circuit interface format.   
     
     
       75. The device of  claim 71 , wherein the signal detector further includes:
   an inter - integrated circuit address content comparator circuit coupled to the video signal lines for comparing with an address in the recorded data such that a set signal is transmitted when there is a match with a pre - set address; and        a monitor - in - system programming control flag unit coupled to the inter - integrated circuit address content comparator circuit for transmitting a start signal after receiving the set signal.     
     
     
       76. The device of  claim 75 , wherein the activation device further includes:
   a monitor - in - system reprogramming initialization circuit for producing a select signal after receiving the start signal; and        a recording pathway isolator for switching over connection from the video pathway to the recording pathway after receiving the select signal and transmitting the recording command and the recorded data via the recording pathway.     
     
     
       77. The device of  claim 71 , wherein the command decoder further includes:
   an inter - integrated circuit interface circuit for receiving and translating the recording command and the recorded data; and        an erase/record command decoder for receiving translated the recording command and recorded data and outputting address, data and erase/read/write signals.     
     
     
       78. The device of  claim 77 , wherein the erase/record command decoder further includes:
   a hidden ROM for holding a program code for the recording command;        a random access memory  ( RAM )  unit for holding the recorded data;        a central processing unit coupled to the hidden ROM, the RAM unit and the inter - integrated circuit interface circuit, wherein the central processing unit receives the recording command and the recorded data passing through the inter - integrated circuit interface circuit and then stores the recorded data in the RAM unit, while the recording command is decoded by referring to the program code in the hidden ROM and then the decoded command is re - transmitted; and        a control register coupled to the central processing unit for receiving the decoded recording command and converting the recording command into an interface control signal or erase/read/write signals, and converting the recorded data stored in the RAM unit into the address and data signals.     
     
     
       79. The device of  claim 77 , wherein the erase/record command decoder is a hardware circuit that separates the recording command picked up by the inter- integrated circuit interface circuit into a plurality of states for ease of decoding and converts the recording command and the recorded data into erase/read/write, address and data signals.   
     
     
       80. The device of  claim 71 , wherein the mode return device further includes:
   a mode return control register for receiving the data and control signals and producing a mode return signal after a reprogramming operation is finished; and        a mode return circuit coupled to the mode return control register and the activation device for sending a stop signal to the activation device after receiving the mode return signal so that the activation device switches over connection from the recording pathway back to the video pathway.     
     
     
       81. The device of  claim 71 , wherein the video signal lines comprise video graphic adapter ( VGA ) signal lines. 
     
     
       82. The device of  claim 71 , wherein the video signal lines comprise digital visual interface ( DVI )  signal lines.   
     
     
       83. The device of  claim 71 , wherein the video signal lines comprise high definition multimedia interface ( HDMI )  signal lines.   
     
     
       84. The device of  claim 71 , wherein the video signal lines comprise component video lines. 
     
     
       85. The device of  claim 71 , wherein the video signal lines comprise S- video lines.   
     
     
       86. The system of  claim 71 , wherein the external ROM unit comprises a flash ROM unit. 
     
     
       87. The system of  claim 71 , wherein the external ROM unit comprises an erasable programmable ROM unit. 
     
     
       88. A system for updating the function of a display, comprising:
   a recording device for storing and outputting a programming signal which comprises a recording command and recorded data;        a video signal port coupled to the recording device for transmitting the recording command and the recorded data; and        a display controller having a programming memory, coupled to the video signal port, wherein if a setting command of the programming signal from the video signal port is correct, the display controller is modified according to the recording command and the recorded data, wherein the video signal port and the display controller are installed in the display system.     
     
     
       89. The system for updating the function of the display as claimed in  claim 88 , wherein the recording device is a computer stage for transmitting the recording command and the recorded data through the video signal port. 
     
     
       90. The system for updating the function of the display as claimed in  claim 88 , the recording device is an inter- integrated circuit interface circuit platform for transmitting the recording command and the recorded data in an inter - integrated circuit interface format.   
     
     
       91. The system for updating the function of the display as claimed in  claim 88 , wherein the display controller further comprises:
   a detecting device coupled to the video signal port for detecting and outputting the recording command and the recorded data;        a starting device coupled to the detecting device for receiving the recording command and the recorded data and then transmitting the recording command and the recorded data when the starting device is switched from a video path to a recording path;        a command decoder connected to the starting device for converting the recording command into a recording signal and the recorded data into data signals by switching the starting device to the recording path, and the command decoder also connected to the programming memory for updating the programming memory according to the recording signal and the data signals; and        a recovery device coupled to the command decoder and the starting device for switching the starting device according to the recording signal or the data signals, the starting device is switching from the recording path to the video path after the data of the programming memory is already updated.     
     
     
       92. The system for updating the function of the display as claimed in  claim 91 , wherein the detecting device further comprises:
   a checking circuit coupled to the video signal port for checking the setting command of the programming signal and then transmitting a setting signal when the checked setting command is correct; and        a programming flag coupled to the checking circuit for setting the display to a programming control mode according to the setting signal and transmitting a programming starting signal.     
     
     
       93. The system for updating the function of the display as claimed in  claim 92 , wherein the starting device further comprises:
   a programming reset generating circuit for generating a selecting signal according to the programming starting signal; and        a recording path separator switched from the video path to the recording path according to the selecting signal and transmitting the recording command and the recorded data via the recording path.     
     
     
       94. The system for updating the function of the display as claimed in  claim 91 , wherein the command decoder comprises:
   an inter - integrated circuit interface circuit for receiving and converting the recording command and the recorded data; and        a recording command decoder for receiving the converted recording command and the recorded data and transmitting the recording signal and the data signals.     
     
     
       95. The system for updating the function of the display as claimed in  claim 94 , wherein the recording command decoder comprises:
   a hidden ROM for storing the program codes of the recording command;        a RAM for storing the recorded data;        a CPU coupled to the hidden ROM, the RAM and the inter - integrated circuit interface circuit for receiving the inter - integrated circuit interface circuit - converting recording command and recorded data, storing the recorded data in the RAM, decoding the recording command according to the program code of the hidden ROM and then sending the decoded recording command; and        a recording control recorder coupled to the CPU for receiving the decoded recording command and converting the decoded recording command into the recording signal and sending the recorded data stored in the RAM according to the data signals.     
     
     
       96. The system for updating the function of the display as claimed in  claim 94 , wherein the function of the recording command decoder can be achieved by a hardware circuit which can divide the recording command received by the inter- integrated circuit interface circuit into a plurality of states to perform the function of decoding and convert the recording command and the recorded data into the recording signal and the data signals.   
     
     
       97. The system for updating the function of the display as claimed in  claim 91 , wherein the recovery device further comprises:
   a recovery control recorder for receiving the data signal and the recording signal and transmitting a recovery signal after recording is achieved; and        a recovery reset circuit coupled to the recovery control recorder and the starting device for transmitting a programming stop signal to switch the starting device from the recording path to the video path when receiving the recovery signal.     
     
     
       98. The system for updating the function of the display as claimed in  claim 88 , wherein the programming memory is a flash ROM. 
     
     
       99. The system for updating the function of the display as claimed in  claim 88 , wherein the programming memory is an electrically erasable programmable read only memory.