Method and apparatus for providing single channel communications

Abstract

A UART including a logic unit is disclosed, wherein the logic unit automatically enables or disables the UART receiver port whenever data is being processed by the UART for wireless transmission. More specifically, a logic unit is connected to a data store, to a transmit FIFO and to a UART processing unit as well as to an external CPU, wherein the logic unit analyzes the logic states of each of the signals from each of the specified connections to determine whether to enable or disable the receiver unit. An inventive method is also disclosed wherein the logic unit only enables the receiver when the data store is empty and the transmitter FIFO is empty and a receiver enable flag is set to true and a half duplex mode of operation has been specified by an external CPU. Otherwise, the logic enables the receiver only when a full duplex mode of operation has been specified and the receiver enable flag is set to a logic one.

1. A UART capable of operating in both full duplex and half duplex mode for providing single channel communications, comprising:
 a transmitter for transmitting signals on a single communications channel;  
 a receiver for receiving signals on the single communications channel;  
 processing means within the UART for indicating whether the UART is operating in a full duplex mode of operation or whether a receiver enable flag has been set; and  
 receiver control circuitry within the UART for disabling the receiver in response to at least one the indication of a  an indication by the processing means that the UART is not operating in the full duplex mode of operation and the indication of the setting of the receiver enable flag an indication by the processing means that the receiver enable flag has not been set.  
 
     
     
       2. The UART of  claim 1  further comprising means for storing data to be transmitted by the transmitter, the means for storing generating a signal indicating when data for transmission is contained therein. 
     
     
       3. The UART of  claim 2  wherein the receiver control circuitry further  disables the receiver in response to the indication by the processing means that the UART is not operating in the full duplex mode of operation, and the storing means generates a signal indicating data for transmission is contained in the storing means for storing . 
     
     
       4. The UART of  claim 2  wherein the means for storing further comprises:
 a data store for queuing data to be transmitted by the transmitter; and  
 a FIFO for passing data between the data store and the transmitter.  
 
     
     
       5. The UART of  claim 4  wherein the receiver control circuitry disables the receiver in response to signals  the indication by the processing means that the UART is not operating in the full duplex mode of operation, and the storing means generates a signal indicating that data is stored within either the data store and  or the FIFO. 
     
     
       6. The UART of  claim 1  wherein the receiver control circuitry further disables the receiver in response to the indication of whether the receiver enable flag has been set. 
     
     
       7. An apparatus for providing single channel communications, comprising:
 a transmitter for transmitting signals on a single communications channel;  
 a receiver for receiving signals on the single communications channel;  
 processing means within the apparatus for generating an indication of at least one of whether the apparatus is in a full-duplex  full duplex mode and whether a receiver enable flag is set;  
 means for storing data to be transmitted by the transmitter, the means for storing generating an indication when  that data for transmission is contained therein; and  
 receiver control circuitry for disabling the receiver in response to at least one of:
 the indications of whetheran indication that the apparatus is not in athe full duplex mode,; 
 the indication of whetheran indication that the receiver enable flag is set,; and  
 the indication of whetheran indication that the means for storing contains data for transmission.  
 
 
     
     
       8. The apparatus of  claim 7  wherein the means for storing further comprises:
 a data store for queuing data to be transmitted by the transmitter; and  
 a FIFO for passing data between the data store and the transmitter.  
 
     
     
       9. The apparatus of  claim 8  wherein the receiver control circuitry disables and enables  the receiver in response to signals indicating  when the apparatus is not in full duplex mode and there is data within either the data store and  or the FIFO, and the receiver control circuitry enables the receiver when the apparatus is either in full duplex mode, or the apparatus is in half duplex mode and the data store and the FIFO are both empty. 
     
     
       10. A control circuit for a UART, comprising:
 means for receiving at least one of a first indicator of whether the UART operates  is operating in a full-duplex  full duplex mode, a second indicator of whether a receiver enable flag is set, and a third indicator of whether data for transmission is stored; and  
 control circuitry within the UART for completely  selectively disabling a receiver responsive to at least one of the first, second and third indicators.  
 
     
     
       11. The control circuit of  claim 10  wherein the control circuitry enables the receiver if the first indicator indicates that the UART is operating in the full duplex mode, and the second indicator indicates that the receiver enable flag is set. 
     
     
       12. The control circuit of  claim 10  wherein the control circuitry disables the receiver if the second indicator indicates that the receiver enable flag is not set. 
     
     
       13. The control circuit of  claim 10  wherein the control circuitry enables the receiver if the first indicator indicates that the UART is not operating in the full duplex mode, and the third indicator indicates that there is no data stored for transmission. 
     
     
       14. The control circuit of  claim 10  wherein the control circuitry disables the receiver if the first indicator indicates that the UART is not operating in the full duplex mode, and the third indicator indicates that there is data stored for transmission.