Flash memory control method, flash memory system using the control method and flash memory device using the control method

Abstract

A method of correcting errors of a flash memory comprises steps of modifying the data of a group of memory units, each having a plurality of flash memory cells adapted to erasing data therefrom and writing data therein, checking for the presence or absence of an error of not properly modifying the data of the group of memory units and determining the completion of proper modification of the data of the group of memory units provided that an error is detected and the error can be corrected.

1. A method of controlling a flash memory system comprising the steps of:
 modifying data of a group of flash memory cells adapted to erasing data therefrom and writing data therein;  
 checking for the presence or absence of an error of not properly modifying said data of said group of memory units  cells; and  
 determining the completion of proper modification of said data of said group of memory units  cells provided that an error is detected and said error can be corrected.  
 
     
     
       2. A method of controlling a flash memory system comprising steps of:
 erasing data written in a group of flash memory cells adapted to erasing data therefrom and writing data therein;  
 reading the data written in said group of memory units  cells having said data erased and checking the completion of proper erasure of said data;  
 counting the number of errors of not being properly erased provided that said data are determined not to be properly erased as a result of said checking step; and  
 determining completion of proper erasure of said data of said group of memory units  cells provided that the counted number of errors is within a correctable range.  
 
     
     
       3. A method of controlling a flash memory system comprising steps of:
 writing data in a group of memory units, each having a plurality of flash memory cells adapted to erasing data therefrom and writing data therein;  
 reading the data written in said group of memory units and checking the completion of proper writing of said data;  
 counting the number of errors of not being properly written provided that said data are determined not to be properly written as a result of said checking step; and  
 determining the completion of proper writing of said data of said group of memory units provided that the counted number of errors is within a correctable range.  
 
     
     
       4. A flash memory system comprising:
 a group of memory units, each having a plurality of flash memory cells adapted to erasing data therefrom and writing data therein;  
 an error detection unit for reading the data written in said group of memory units and detecting errors during data modification; and  
 an error judgement section for counting the number of errors detected by said error detection unit and determining the completion of proper data modification of data provided that the number of errors detected by said error detection unit is not greater than a number which can be corrected in accordance with an error check code.  
 
     
     
       5. A flash memory system comprising:
 a memory cluster having a plurality of flash memory cells adapted to erasing data therefrom and writing data therein;  
 at least one or more than one memory sectors constituting said memory cluster;  
 a flash memory control unit for ordering erasure of the data written in said memory cluster;  
 an error detection/correction unit for detecting erase errors in the data read from said memory cluster and correcting erase errors up to n (n is a number of memory cells in a memory sector, that can be corrected in accordance with an error check code) attribute  attributable to memory cells; and  
 an error judgement section for counting the erase errors of each memory sector and determining the completion of proper data erasure provided that the completion of proper data erasure provided that  is judged by the number of memory cells storing unerased data is not greater than m (1≦m≦n) in each and every memory sector.  
 
     
     
       6. A flash memory system comprising:
 a memory cluster having a plurality of flash memory cells adapted to erasing data therefrom and writing data therein;  
 at least one or more than one memory sectors constituting said memory cluster;  
 a flash memory control unit for ordering erasure of the data written in said memory cluster;  
 an error detection/correction unit for detecting erase errors in the data read from said memory cluster and correcting erase errors up to n (n is a number of symbols in a memory sector that can be corrected in accordance with an error check code (1 symbol=k bits, k≧2)) symbols attributable to the data;  
 a counter unit for counting the number of symbols showing erase errors and contained in each memory sector; and  
 an error judgement section for determining the completion of proper data modification provided that the number of symbols showing erase errors is not greater than m (1≦m≦n) in each and every memory sector.  
 
     
     
       7. A flash memory system comprising:
 a memory cluster comprising a plurality of external flash memory cells;  
 at least one or more than one memory sector constituting said memory cluster;  
 a flash memory control unit for ordering writing of the data in said memory sectors;  
 an error detection/correction unit for detecting errors in the data read from said memory cluster and correcting erase errors up to n (n is the number of memory cells in a memory sector, that can be corrected in accordance with an error check code) attributable to flash memory cells; and  
 an error judgement section for counting the number of memory cells defective in terms of writing and contained in each memory sector and determining the completion of proper data writing provided that the number of memory cells defective in terms of writing is not greater than n in each and every memory sector.  
 
     
     
       8. A flash memory system comprising:
 memory sectors having a plurality of flash memory cells;  
 a flash memory control unit for ordering writing of the data in each of said memory sectors;  
 an error detection/correction unit for detecting write errors in the data read from said memory cluster and correcting write errors up to n (n is a number of symbols in a memory sector, that can be corrected in accordance with an error check code (1 symbol=k bits, k≧2)) symbols (1 symbol=k bits, k≧2)  attributable to the data; and  
 an error judgement section for counting the number of symbols defective in terms of writing as detected by said detection/correction unit aid  and determining the completion of proper data modification provided that the number of symbols showing errors is not greater than m (1≦m≦n) in each and every memory sector.  
 
     
     
       9. A flash memory system comprising:
 a memory cluster comprising a plurality of external flash memory cells;  
 at least one or more than one memory sectors constituting said memory cluster;  
 a flash memory control unit for ordering writing of the data in said memory sectors;  
 an error detection/correction unit for detecting write errors in the data read from said memory cluster and correcting write errors up to n (n is a number of bits in a memory sector, that can be corrected in accordance with an error check code) bits attributable to the data; and  
 an error judgement section for counting the number of bits showing write errors and determining the completion of proper data writing provided that the number of bits showing write errors is not greater than m (1≦m≦n) bits in each and every memory sector.  
 
     
     
       10. A flash memory system comprising:
 a memory unit, including a plurality of flash memory cells, for storing data which can be electrically changed;  
 a control circuit for reading out the data stored in said memory unit and for controlling said memory unit in order to change the data stored in said memory unit;  
 an error detection and correction unit for detecting whether an error has been occurred  exists in read-out data read out by said control circuit and for correcting errors in the read-out data; and  
 an error judgement section, being implemented independent of said error detection and correction unit, for counting the number of failure data regarded as having not been successfully stored in the memory unit;  
 wherein said flash memory system settles that changing of data has been successfully done if the number of failure data is not larger than a predetermined number, said predetermined number satisfying the condition that the predetermined number of failure data can be corrected by said error detection and correction unit.  
 
     
     
       11. The flash memory system according to  claim 10 , wherein said predetermined number is one. 
     
     
       12. The flash memory system according to  claim 10 , wherein a data length of each data stored in said memory unit is one bit. 
     
     
       13. The flash memory system according to  claim 10 , wherein a data length of each data stored in said memory unit is larger than one bit. 
     
     
       14. A flash memory device comprising:
 a memory unit, including a plurality of flash memory cells, for storing data which can be electrically changed;  
 a control circuit for reading out the data stored in said memory unit and for controlling said memory unit in order to change the data stored in said memory unit;  
 an error judgement section, being included in said control circuit, for counting the number of failure data regarded as having not been successfully stored in the memory unit;  
 wherein, if the number of failure data is not larger than a predetermined number, said control circuit outputs status data which means that changing of data has been successfully done, wherein the counting is responsive to the changing of data during an erasing or a writing operation.  
 
     
     
       15. The flash memory device according to  claim 14 , wherein said predetermined number is one. 
     
     
       16. The flash memory device according to  claim 14 , wherein a data length of each data stored in said memory unit is one bit. 
     
     
       17. The flash memory device according to  claim 14 , wherein a data length of each data stored in said memory unit is larger than one bit. 
     
     
       18. A flash memory device comprising:
 a group of memory units, each having a plurality of flash memory cells adapted to erasing data therefrom and writing data therein; and  
 an error judgement section for determining the completion of proper data modification of data provided that the number of errors detected during data modification by an error detection/correction unit detecting/correcting errors in the data written in said group of memory units is not greater than a number of errors within a correctable range.  
 
     
     
       19. A flash memory device comprising:
 a group of memory units, each having a plurality of flash memory cells adapted to erasing data therefrom and writing data therein;  
 an error detection unit for reading the data from said group of memory units and detecting errors during data modification; and  
 an error judgement section for counting the number of errors detected by said error detection unit and determining the completion of proper data modification of data provided that the number of errors detected by said error detection unit is not greater than a number which can be corrected in accordance with an error check code.  
 
     
     
       20. A computer-readable recording medium storing a program for realizing in a computer:
 a function of ordering modification of data to an external memory device containing a group of memory units, each having a plurality of flash memory cells adapted to erasing data therefrom and writing data therein; and  
 a function of checking for the presence or absence of an error of not properly modifying said data of said group of memory units and determining the completion of proper modification of said data of said group of memory units provided that an error is detected and said error can be corrected.  
 
     
     
       21. A computer-readable recording medium storing a program for realizing in a computer; :
 a function of ordering erasure of the data written in a group of memory units, each having a plurality of flash memory cells adapted to erasing data therefrom and writing data therein; and  
 a function of reading the data written in said group of memory units having said data erased and checking the completion of proper erasure of said data, counting the number of errors of not being properly erased provided that said data are not properly erased as a result of said checking step and determining the completion of proper erasure of said data of said group of memory units provided that the counted number of errors is within a correctable range.  
 
     
     
       22. A computer-readable recording medium storing a program for realizing in a computer; :
 a function of ordering writing of data written in a group of memory units, each having a plurality of flash memory cells adapted to erasing data therefrom and writing data therein; and  
 a function of reading the data written in said group of memory units and checking the completion of proper writing of said data counting the number of errors of not being properly written provided that said data are not properly written as a result of said checking step and determining the completion of proper writing of said data of said group of memory units provided that the counted number of errors is within a correctable range.  
 
     
     
       23. A flash memory system comprising:
 a flash memory cell array;  
 a control circuit for erasing data from designated part of said memory cell array, for writing data into given part of said memory cell array, and for reading data from said designated or given part of said memory cell array, thereby it can be detected how many errors have been occurred within said designated or given part of said memory cell array after erasing or writing;  
 a counter for counting the number of the errors based on data read by said control circuit after the erasing or writing;  
 an error judgement section for outputting information that it is successfully erased or written if the number counted is smaller than a number which can be corrected in accordance with an error check code; and  
 an error detection/correction unit equipped beside said counter and said error judgement section for generating said error check code accompanying with data to be written into said given part of said memory cell array, said error check code being also written into said given part, and for correcting errors existing in data read from said designated or given part of said memory cell array.  
 
     
     
       24. The flash memory system according to  claim 23 , wherein said number that can be corrected in accordance with an error check code, that  is one. 
     
     
       25. The flash memory system according to  claim 23 , wherein data stored in said memory cell array is divided into a plurality of symbols (1 symbol=k bits; k>0), said counter counts the number of the errors in increments of one of said symbols, and if any one bit among one symbol is failed in erasing or writing, said counter assumes that such symbol is an error. 
     
     
       26. The flash memory system according to  claim 25 , wherein said number that can be corrected in accordance with an error check code is one. 
     
     
       27. A flash memory device comprising:
 a flash memory cell array;  
 a control circuit for erasing data from a designated part of said memory cell array, for writing input data and check code incidental to said input data into a given part of said memory cell array, said input data being also input from external to the flash memory device, and for reading data from said designated or given part of said memory cell array, thereby  whereby it can be detected how many errors have been occurred  exist within said designated or given part of said memory cell array after erasing or writing;  
 a counter for counting the number of the errors based on data read by said control circuit after the erasing or writing; and  
 an error judgement section for outputting information that it  a part of the said memory cell array is successfully erased or written if the number counted is smaller than a number that can be corrected in accordance with an error check code;  
 wherein if read instruction and address are input to the flash memory device, the input data and the check code stored in part of said memory cell array addressed by said address are read out by said control circuit and output to  external to the flash memory device without any modification.  
 
     
     
       28. The flash memory device according to  claim 27 , wherein said number that can be corrected in accordance with an error check code within a correctable range is one. 
     
     
       29. The flash memory device according to  claim 27 , wherein data stored in said memory cell array is divided into a plurality of symbols (1 symbol=k bits; k>0), said counter counts the number of the errors in increments of one of said symbols, and if any one bit among one symbol is failed in erasing or writing, said counter assumes that such symbol is an error. 
     
     
       30. The flash memory device according to  claim 29 , wherein said number that can be corrected in accordance with an error check code, that  is one. 
     
     
       31. The method of  claim 1 , wherein said modifying data includes writing error check code data to said group of flash memory cells prior to checking for the presence or absence of error. 
     
     
       32. The method of  claim 1 , wherein said group of flash memory cells is a sector for writing data and is a cluster for erasing data, the cluster comprising a plurality of sectors. 
     
     
       33. The method of  claim 1 , wherein said flash memory cells are each capable of handling multi- bit data.   
     
     
       34. The method of  claim 1 , further comprising storing redundant address information in said group of flash memory cells. 
     
     
       35. The method of  claim 2 , wherein said group of flash memory cells is a sector for writing data and said group of flash memory cells is a cluster for erasing data and wherein the cluster includes a plurality of sectors. 
     
     
       36. The method of  claim 3 , wherein said writing data includes writing error check code data to said group of flash memory units prior to checking for the completion of proper writing. 
     
     
       37. The method of  claim 3 , wherein said group of flash memory units is a sector for writing data. 
     
     
       38. The method according to  claim 3 , wherein said flash memory units are each capable of handling multi- bit data.   
     
     
       39. The method of  claim 3 , further comprising storing redundant address information in said group of flash memory units. 
     
     
       40. The flash memory system of  claim 4 , wherein the error judgement section determines the completion of proper data modification if the number of errors detected is less than the number which can be corrected in accordance with an error check code. 
     
     
       41. The flash memory system of  claim 4 , wherein said group of memory units stores error check code data for said group of memory units. 
     
     
       42. The flash memory system according to  claim 4 , wherein said flash memory cells are each capable of handling multi- bit data.   
     
     
       43. The flash memory system of  claim 4 , further comprising storing redundant address information in said group of flash memory units. 
     
     
       44. The system according to  claim 10 , wherein the flash memory system is a flash memory card that includes an MPU. 
     
     
       45. The system according to  claim 10 , wherein the memory unit includes a memory cell array of NAND type cells and includes the error judgement section. 
     
     
       46. The system according to  claim 45 , wherein the memory unit is capable of handling data in a four- valued system.   
     
     
       47. The system according to  claim 45 , wherein a unit of erasing data in the memory cell array is a cluster, a unit of writing data to the memory cell array is a sector, and the cluster includes a plurality of sectors. 
     
     
       48. The system according to  claim 47 , wherein the sector includes a first portion for storing user data and a second portion for storing error check codes. 
     
     
       49. The system according to  claim 48 , wherein the sector includes a third portion for storing a logical address. 
     
     
       50. The system according to  claim 49 , wherein a number of bits in the error check codes is equal to or greater than  86  bits. 
     
     
       51. The system according to  claim 50 , wherein two neighboring clusters share a source line. 
     
     
       52. The system according to  claim 51 , wherein a selection transistor is connected to the source line. 
     
     
       53. The system according to  claim 52 , wherein the sector includes a total of  2 , 112  memory cells. 
     
     
       54. The system according to  claim 53 , wherein the memory unit is capable of handling data in a four- valued system.   
     
     
       55. The system of  claim 10 , wherein said memory unit stores redundant addresses. 
     
     
       56. The flash memory device according to  claim 14 , wherein the control circuit outputs status data which means that changing of data has been successfully done even though the number of failure data is more than zero. 
     
     
       57. The flash memory device according to  claim 56 , wherein the memory unit includes a memory cell array of NAND type cells. 
     
     
       58. The flash memory device according to  claim 57 , wherein the memory unit is capable of handling data in a four- valued system.   
     
     
       59. The flash memory device according to  claim 57 , wherein a unit of erasing data in the memory cell array is a cluster, a unit of writing data to the memory cell array is a sector, and the cluster includes a plurality of sectors. 
     
     
       60. The flash memory device according to  claim 59 , wherein the sector includes a first portion for storing user data and a second portion for storing error check codes. 
     
     
       61. The flash memory device according to  claim 60 , wherein the sector further includes a third portion for storing a logical address. 
     
     
       62. The flash memory device according to  claim 61 , wherein a number of bits in the error check codes is equal to or more than  86  bits. 
     
     
       63. The flash memory device according to  claim 62 , wherein two neighboring clusters share a source line. 
     
     
       64. The flash memory device according to  claim 63 , wherein a selection transistor is connected to the source line. 
     
     
       65. The flash memory device according to  claim 64 , wherein the sector includes a total of  2 , 112  memory cells. 
     
     
       66. The flash memory device according to  claim 65 , wherein the memory unit is capable of handling data in a four- valued system.   
     
     
       67. The flash memory device according to  claim 14 , wherein the memory unit stores redundant addresses.