Method of multi-level storage in DRAM and apparatus thereof

Abstract

A method of processing data having one of four voltage levels stored in a DRAM cell is comprised of sensing whether or not the data voltage is above or below a voltage level midway between a highest and a lowest of the four levels, setting the voltage on a reference line higher than the lowest and lower than the next highest of the four levels in the event the data voltage is below the midway voltage level, and setting the voltage on the reference line higher than the second highest and lower than the highest of the four levels in the event the data voltage is above the midway point, and sensing whether the data voltage is higher or lower than the reference line, whereby which of the four levels the data occupies is read.

1. A method of processing data having one of four voltage levels stored in a DRAM cell comprising:
 (a) sensing whether or not the data voltage is above or below a voltage level midway between a highest and a lowest of said four levels,    (b) setting the voltage on a reference line higher than the lowest and lower than the next highest of said four levels in the event the data voltage is below said midway voltage level, and setting the voltage on the reference line higher than the second highest and lower than the highest of said four levels in the event the data voltage is above said midway voltage level, and    (c) sensing whether the data voltage is higher or lower than the reference line, whereby which of the four levels the data occupies is read.    
     
     
       2. A method as defined in  claim 1  in which the voltage on the reference line is set at approximately one half the voltage difference between either of the lowest or highest voltage level and the adjacent one of the four voltage levels. 
     
     
       3. A method as defined in  claim 1  in which said four levels are at 0, ⅓, ⅔ and 1 times a power supply voltage scaled by the cell to bitline capacitance ratio, and in which the voltage on the reference line in step (b) is set at either 1/6 or 5/6 the power supply voltage in step (b) scaled by the cell to bitline capacitance ratio. 
     
     
       4. A method as defined in  claim 1  including charging a dummy capacitor to a level representing whether or not said data is above or below said midway voltage, and setting the voltage on the reference line by establishing a voltage level thereon which is midway between the highest and lowest of said four levels, then raising or lowering the voltage level thereon by dumping the charge from said dummy capacitor thereon. 
     
     
       5. A method of processing data having one of plural levels stored in a DRAM cell capacitor comprising:
 (a) dumping the charge of the cell capacitor on a first conductor of a pair of conductors of a folded bitline,    (b) maintaining the other conductor of said pair of conductors split into other sub-bitline conductors and charging each of said other sub-bitline conductors to an intermediate voltage,    (c) splitting said first of said pair of conductors into first sub-bitline conductors,    (d) sensing one of said sub-bitline conductors to determine whether the charge of said cell has a higher voltage than the intermediate voltage of one of said other sub-bitline conductors and providing a logic level result signal,    (e) storing said logic level result signal in a dummy cell capacitor,    (f) setting a charge storage capacitor and all of the sub-bitlines other than a first sub-bitline conductor on which the charges of cell capacitor was dumped, at to a predetermined voltage,    (g) dumping charge stored in the dummy cell capacitor on said sub-bitlines conductors other than the first sub-bitline conductor to which the charge of the cell capacitor was dumped, and on said charge storage capacitor together, thereby varying the predetermined voltage stored thereon to a degree related to the capacities of said dummy cell capacitor, said charge storage capacitor and said predetermined voltage, to a level above or below the intermediate level,    (h) isolating the sub-bitlines,    (i) applying said intermediate voltage to one of said other sub-bitline conductors,    (j) comparing the cell voltage on one sub-bitline with the voltage on said other sub-bitline carrying said level above or below the intermediate level to obtain a first logic bit, and comparing the voltages carried by the other sub-bitlines to obtain a second logic bit,    whereby said first and second logic bits are indicative of one of four states corresponding to one of said plural levels stored in the DRAM cell.    
     
     
       6. A method as defined in  claim 5  in which said intermediate and said predetermined voltages are the same. 
     
     
       7. A method as defined in  claim 6  in which said intermediate and predetermined voltages are the same midpoint voltage between a highest and lowest voltage state representative of four logical states. 
     
     
       8. A method as defined in  claim 7 , including the further steps of short circuiting two or three of the sub-bitlines to share charge thereon and establish a common voltage level, and storing said shared charge corresponding to the common voltage level on said cell, whereby a restore or write operation results. 
     
     
       9. A method as defined in  claim 7 , including the further steps of writing logic voltage levels to each of the sub-bitline conductors, short circuiting two or three of the sub-bitlines to share charge thereon and establish a common voltage level, and storing said shared charge corresponding to the common voltage level on said cell, whereby a write operation results. 
     
     
       10. A multi- bit DRAM cell, comprising:      a cell capacitor in which one of a plurality of data voltage values is maintained;        means for precharging subbitlines of a pair of bitlines, the pair of bitlines being subdivided into a plurality of subbitlines;        a plurality of switches for interconnecting the subbitlines;        a plurality of sensing amplifiers, each sensing amplifier associated with and switchably connected to a pair of subbitlines;        means for dumping a stored charge onto a precharged subbitline of at least one pair of subbitlines to produce a sensing voltage; and        means for adjusting a reference voltage responsive to a last determined bit.     
     
     
       11. The multi- bit DRAM cell of    claim 10   , wherein the switches are FET switches.   
     
     
       12. The multi- bit DRAM cell of    claim 11   , wherein the means for adjusting the reference voltage comprises:      a dummy capacitor, in which a charge indicative of previously determined bits is stored; and        at least one second cell capacitor having a capacitance such that upon dumping the charge stored in the dummy capacitor into said at least one second cell capacitor, the adjusted reference voltage is established, said adjusted reference voltage being one of a plurality of predetermined reference voltage levels.     
     
     
       13. The multi- bit DRAM cell of    claim 11   , wherein the pair of bitlines is divided into a number of subbitlines, said number responsive to the number of data voltage values.   
     
     
       14. The multi- bit DRAM cell of    claim 11   , wherein the DRAM cell is capable of operating in either of two modes, a first mode being a one bit per cell DRAM, and a second mode being a multibit per cell DRAM.   
     
     
       15. A method for storing a multi- bit value in a DRAM cell, the method comprising:      storing a charge in a cell capacitor, the stored charge producing one of a plurality of data voltage values;        precharging subbitlines of a pair of bitlines to one of a plurality of predetermined reference voltage levels;        dumping the stored charge onto a precharged subbitline of at least one pair of subbitlines to produce a sensing voltage;        determining a bit of the multi - bit value by comparing the sensing voltage to a reference voltage;        for each additional bit,      adjusting the reference voltage responsive to a last determined bit; and        determining the additional bit by comparing the sensing voltage to the adjusted reference voltage.       
     
     
       16. The method of  claim 15 , wherein adjusting the reference voltage comprises:
   storing a charge in a dummy capacitor, said charge being indicative of previously determined bits;        charging at least one second cell capacitor to the reference voltage; and        dumping the charge stored in the dummy capacitor onto a plurality of subbitlines, and sharing said charge with the at least one second cell capacitor, the at least one second cell capacitor having a capacitance such that the adjusted reference voltage is established, said adjusted reference voltage being one of the plurality of predetermined reference voltage levels.     
     
     
       17. The method of  claim 15 , wherein the pair of bitlines is divided into a number of subbitlines, said number responsive to the number of data voltage values. 
     
     
       18. The method of  claim 15 , wherein the DRAM cell is capable of operating in either of two modes, a first mode being a one bit per cell DRAM, and a second mode being a multibit per cell DRAM. 
     
     
       19. The method  claim 15 , wherein adjusting the reference voltage is in the direction of a last sensed bit.