USRE40053EExpiredUtility

Delay circuit having delay time adjustable by current

Assignee: FUJITSU LTDPriority: Jan 31, 2000Filed: Apr 15, 2005Granted: Feb 12, 2008
Est. expiryJan 31, 2020(expired)· nominal 20-yr term from priority
Inventors:Satoshi Eto
H03K 5/133H03K 2005/00039H03K 2005/00202G11C 8/00
42
PatentIndex Score
0
Cited by
18
References
11
Claims

Abstract

A delay circuit includes a delay part delaying a signal by a delay time which can be varied based on a control current, and a control current adjustment circuit adjusting the control current so that the delay time changes linearly based on a variation in a resistance value.

Claims

exact text as granted — not AI-modified
1. A delay circuit comprising:
 a delay part delaying a signal by a delay time which is varied based on a control current; and  
 a control current adjustment circuit adjusting the control current so that the delay time changes linearly based on a variation in a resistance value,  
 wherein the control current adjustment circuit comprises: 
 a first resistance unit generating a first voltage; and  
 a second resistance unit comprising a second variable resistor in which the resistance value of the second variable resistor varies stepwisely or discretely but linearly as a whole so that the control current adjusting circuit controls the control current based on the resistance value of the second variable resistor for generating a second voltage; and wherein 
 the control current adjusting circuit controls the control current based on the first and second voltages;  
 the first resistance unit comprises a fixed resistor and a first variable resistor; and  
 the second resistance unit comprises a  the second variable resistor having a resistance value equal to that of the first variable resistor.  
 
 
 
     
     
       2. The delay circuit as claimed in  claim 1 , wherein the delay part comprises a logic circuit which delays the signal by the delay time in accordance with the control current. 
     
     
       3. The delay circuit as claimed in  claim 1 , wherein each of the first and second variable resistors has  are variable over a plurality of discrete resistance values. 
     
     
       4. A delay circuit comprising:
 a delay part delaying a signal by a delay time which is varied based on a control current; and  
 a control current adjustment circuit adjusting the control current so that the delay time changes linearly based on a variation in a resistance value, wherein the control circuit adjustment circuit comprises: 
 a first resistance unit generating a first voltage, the first resistance unit comprising a first fixed resistor and a first variable resistor;  
 a second resistance unit generating a second voltage, the second resistance unit comprising a second variable resistor; and  
 a control current controlling circuit controlling the control current based on the first and second voltages.  
 
 
     
     
       5. The delay circuit as claimed in  claim 4 , wherein the  each of the first and second variable resistors are variable resistor has  over a plurality of discrete resistance values. 
     
     
       6. A semiconductor device comprising:
 a delay circuit delaying a given signal; and  
 an internal circuit operating using a delayed given signal from the delay circuit, the delay circuit comprising: 
 a delay part delaying a  the given signal by a delay time which can be  is varied based on a control current; and  
 a control current adjustment circuit adjusting the control current so that the delay time changes linearly based on a variation in a resistance value,  
 wherein the control current adjustment circuit comprises: 
 a first resistance unit generating a first voltage; and  
 a second resistance unit comprising a second variable resistor in which the resistance value of the second variable resistor varies stepwisely or discretely but linearly as a whole so that the control current adiusting  adjusting circuit controls the control current based on the resistance value of the second variable resistor for generating a second voltage; and wherein  
 the control current adjusting circuit controls the control current based on the first and second voltages;  
 the first resistance unit comprises a fixed resistor and a first varable  variable resistor; and  
 the second resistance unit comprises a  the second variable resistor having a resistance value equal to that of the first variable resistor.  
 
 
 
     
     
       7. The semiconductor device as claimed in  claim 6 , wherein each of the first and second variable resistors has  are variable over a plurality of discrete resistance values. 
     
     
       8. The sermiconductor  semiconductor device as claimed in  claim 6 , wherein the delay part comprises a logic circuit which delays the given signal by the delay time in accordance with the control current. 
     
     
       9. A semiconductor device comprising:
 a delay circuit delaying a given signal; and  
 an internal circuit operating using a delayed given signal from the delay circuit, the delay circuit comprising: 
 a delay part delaying a  the given signal by a delay time which can be  is varied based on a control current; and  
 a control current adjustnent  adjustment circuit adjusting the control current so that the delay time changes linearly based on a variation in a resistance value, wherein the control current adjustment circuit comprises: 
 a first resistance unit generating a first voltage, the first resistance unit comprising a first fixed resistor and a first variable resistor;  
 a second resistance unit generating a second voltage, the second resistance unit comprising a second variable resistor; and  
 a control current generating circuit generating the control current based on the first and second voltages.  
 
 
 
     
     
       10. The semiconductor device as claimed in  claim 9 , wherein the variable resistor has  each of the first and second variable resistors are variable over a plurality of discrete resistance values. 
     
     
       11. The semiconductor device as claimed in  claim 9 , wherein the given signal is an external clock, and the internal circuit is a data input/output circuit.

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