Compressed image decompressing device

Abstract

An image processing device which processes a portion of the decompression process including a lot of comparatively complex operations like an inverse discrete cosine transform by software with using a high-performance, general-purpose processor capable of parallel processing, and the other portion of the decompression process which is compara- tively simple but requires frequent access to a memory, e.g., when other frame data is to be read out for processing of encoded interframe predictive image data, or is compara- tively simple but substantially hard to process in parallel, e.g., when variable length coded pixel values are to be decoded, by hardware with the use of a specialized periph- eral circuit.

1. An image processing device comprising:
 a processor which includes an instruction decoder for decoding instructions of an image processing program and an instruction executing unit for executing the instructions responsive to outputs from said instruction decoder, and outputs the execution result by said instruction executing unit; and  
 a data loader, connected to said processor, which includes a data reading unit for reading image data of fixed length codes, an adding unit, connected to the data reading unit, for adding image data of at least two adjacent pixels of the image data read by the data reading unit, and a data writing unit, connected to the adding unit, for writing the addition result by the adding unit into said processor,  
 wherein said processor is configured to perform a process of decoding a first kind of image data of variable length codes to a second kind of image data of fixed length codes, a process of transforming the second kind of image data to a third kind of image data, a process of performing a prescribed operation between the third kind of image data and the addition result written by said data loader.  
 
     
     
       2. An image processing device comprising:
 a memory for storing data used for executing an image processmg program;  
 a processor, connected to said memory, which includes an instruction decoder for decoding instructions of the image processing program and an instruction executing unit for executing the instructions responsive to outputs from said instruction decoder, and performs a pre- scribed operation according to the instructions described in the image processing program and outputs the operation result; and  
 a data loader, connected to said memory, which includes a data reading unit for reading image data of fixed length codes, an adding unit, connected to the data reading unit, for adding image data of at least two adjacent pixels read by the data reading unit, and a data writing unit, connected to the adding unit, for writing the addition result by the adding unit into said memory, wherein said processor is configured to perform a process of decoding a first kind of image data of variable length codes to a second kind of image data of fixed length codes, a process of transforming the sec- ond kind of image data to a third kind of image data, a process of performing a prescribed operation between the third kind of image data and the addition result written by said data loader into said memory.  
 
     
     
       3. An image processing device comprising:
 a memory for storing data used for executing an image processmg program;  
 a processor, connected to said memory, which includes an instruction decoder for decoding instructions of the image processing program and an instruction executing unit for executing the instructions responsive to outputs from said instruction decoder, and performs a pre- scribed operation according to the instructions described in the image processing program and outputs the operation result; and  
 a data loader, connected to said memory, which includes a data reading unit for reading image data of fixed length codes for the half pel or for the full pel, an adding unit, connected to the data reading unit, for adding image data of at least two adjacent pixels of the image data of fixed length codes read by the data reading unit in case of processing of image data for the half pel, while extending a bit width of the image data of fixed length codes read by the reading unit in case of processing of image data for the full pel, and a data writing unit, connected to the adding unit, for writing to said memory first data of the addition result by the adding unit or second data extended in the bit width by the adding unit,  
 wherein said processor is configured to perform a process of decoding a first kind of image data of variable length codes to a second kind of image data of fixed length codes, a process of transforming the second kind of image data to a third kind of image data, a process of performing a prescribed operation between the third kind of image data and the first or second data by reading the first data from said memory in case of processing of the image data for the half pel or the second data from said memory in case of processing of the image data for the full pel.  
 
     
     
       4. An image processing device comprising:
 a first memory and a second memory for storing data used for executing an image processing program;  
 a first processor, connected to the first memory, which includes a first instruction decoder for decoding instructions of the image processing program, and a first instruction executing unit for executing the instruc- tions responsive to outputs from the first instruction decoder, and outputs the execution result by the first instruction executing unit;  
 a second processor, connected to the second memory, which includes a second instruction decoder for decod- ing the instructions of the image processing program and a second instruction executing unit for executing the instructions responsive to outputs from the second instruction decoder, and outputs the execution result by the second instruction executing unit;  
 a variable length code decoder, connected to the first and second memories, which decodes a first kind of image data of variable length codes to a second kind of image data of fixed length codes and outputs the decoding result to the first or second memory; and  
 a data loader, connected to the first and second memories, which outputs image data of fixed length codes to the first or second memory,  
 wherein said first and second processors respectively are configured to perform a process of reading the second kind of image data from the first or second memory and transforming the second kind of image data to a third kind of image data, and a process of reading image data of fixed length codes from said first or second memory and performing a prescribed operation between the third kind of image data and the image data of the fixed length codes.  
 
     
     
       5. An image processing device as set forth in  claim 4 , further comprising a third memory, connected to the first and second processors, for storing instructions of the image processing program, wherein the first and second processors further include, respectively, means for operating in parallel with each other by reading out the instructions from the third memory. 
     
     
       6. An image processing device comprising:
 a processor which includes an instruction decoder for decoding instructions of the image processing program and an instruction executing unit for executing the instructions responsive to outputs from said instruction decoder, and outputs the execution result by said instruction executing unit;  
 a variable length code decoder, connected to said processor, which decodes a first kind of image data of variable length codes to a second kind of image data of fixed length codes and outputs the second kind of image data to said processor; and  
 a data loader, connected to said processor, which includes a data reading unit for reading image data of fixed length codes, an adding unit, connected to the data reading unit, for adding image data of at least two adjacent pixels of the image data of fixed length codes, and a data writing unit, connected to the adding unit, for writing the addition result by the adding unit into said processor,  
 wherein said processor is configured to perform a process of transforming the second kind of image data output from said variable length code decoder to a third kind of image data, and a process of performing a prescribed operation between the third kind of image data and the addition result written by said data loader.  
 
     
     
       7. An image processing device comprising:
 a memory for storing data used for executing an image processmg program;  
 a processor, connected to said memory, which includes an instruction decoder for decoding instructions of the image processing program and an instruction executing unit for executing the instructions responsive to outputs from said instruction decoder, and outputs and execu- tion result by said instruction executing unit;  
 a variable length code decoder, connected to said memory, which decodes a first kind of image data of variable length codes to a second kind of image data of fixed length codes and outputs the second kind of image data to said memory; and  
 a data loader, connected to said memory, which includes a data reading unit for reading image data of fixed length codes, an adding unit, connected to the data reading unit, for adding image data of at least two adjacent pixels of the image data of fixed length codes read by the data reading unit, and a data writing unit connected to the adding unit, for writing the addition result by the adding unit into said memory,  
 wherein said processor is configured to perform a process of reading the second kind of image data from said memory and transforming the second kind of image data to a third kind of image data, and a process of performing a prescribed operation between the third kind of image data and the addition result read from said memory.  
 
     
     
       8. An image processing device comprising:
 a first and second memories for storing data used for executing an image processing program;  
 a processor, connected to the first memory, which includes an instruction decoder for decoding instructions of the image processing program and a first instruction executing unit for executing the instructions responsive to outputs from the first instruction decoder, and out- puts the execution result by the first instruction execut- ing unit;  
 a second processor, connected to the second memory, which includes a second instruction decoder for decod- ing the instructions of the image processing program and a second instruction executing unit for executing the instructions responsive to outputs from the second instruction decoder, and outputs the execution result by the second instruction executing unit;  
 a variable length code decoder, connected to the first and second memories, which decodes a first kind of image data of variable length codes to a second kind of image data of fixed length codes and outputs the decoding result to the first and second memory;  
 a data loader, connected to the first and second memories, which includes a data reading unit for reading image data of fixed length codes, an adding unit, connected to the data reading unit, for adding image data of at least two adjacent pixels of the image data of fixed length codes read by the data reading unit, and a data writing unit connected to the adding unit, for writing the addition result by the adding unit to the first and second memory,  
 wherein said first and second processors respectively is configured to perform a process of reading the second kind of image data from the first or second memory and transforming the second kind of image data to a third kind of image data, and a process of reading the addition result from said first or second memory and performing a prescribed operation between the third kind of image data and the addition result.  
 
     
     
       9. An image processing device as set forth in  claim 8 , further comprising a third memory, connected to the first and second processors, for storing instructions of the image processing program, wherein the first and second processors further include, respectively, means for operating in parallel with each other by reading out the instructions from the third memory. 
     
     
       10. An image processing device comprising:
 a memory for storing data used for executing an image processmg program;  
 a read-only memory for storing the image processing program;  
 a processor, connected to said memory and said read only memory, which includes an instruction decoder for decoding instructions of the image processing program and an instruction executing unit for executing the instructions responsive to outputs from said instruction decoder, and outputs the execution result by said instruction executing unit;  
 a variable length code decoder, connected to said memory, which decodes a first kind of image data of variable length codes to a second kind of image data of fixed length codes and outputs the second kind of image data to said memory; and  
 a data loader, connected to said memory, which includes an adding unit that adds image data of at least two adj acent pixels read by the data loader and outputs image data of fixed length codes to said memory,  
 wherein said processor is configured to perform a process of reading the second kind of image data from said memory and transforming the second kind of image data to a third kind of image data, and a process of reading image data of fixed length codes from said memory and performing a prescribed operation between the third kind of image data and the image data of fixed length codes.  
 
     
     
       11. An image processing device comprising:
 first and second memories for storing data used for executing an image processing program;  
 a processor, connected to the first and second memories, which includes an instruction decoder for decoding instructions of the image processing program and an instruction executing unit for executing the instructions responsive to outputs from said instruction decoder, and outputs the execution result by said instruction executing unit;  
 a variable length code decoder, connected to the first memory, which decodes a first kind of image data of variable length codes to a second kind of image data of fixed length codes and outputs the second kind of image data to the first memory; and  
 a data loader, connected to the second memory, which includes an adding unit that adds image data of at least two adjacent pixels read by the data loader and outputs image data of fixed length codes to the second memory,  
 wherein said processor is configured to perform a process of reading the second kind of image data from the first memory and transforming a second kind of image data to a third kind of image data, and a process of reading image data of fixed length codes from the second memory and performing a prescribed operation between the third kind of image data and the image data of fixed length codes.  
 
     
     
       12. An image processing device comprising:
 a processor which includes an instruction decoder for decoding instructions of an image processing program and an instruction executing unit for  for executing the instructions responsive to outputs for  from said instruction decoder, and outputs the execution result by said instruction executing unit; and  
 a variable length code decoder, connected to said processor, which decodes a first kind of image data of variable length codes to a second kind of image data of fixed length codes, and outputs the second kind of data to said processor,  
 wherein said processor is configured to perform a process of transforming the second kind of image data output from said variable length code decoder to a third kind of image data according to the image processing program,  
 and wherein the processor includes a register having a first portion and a second portion for storing two image data each comprising a number (n) of bits, and the instruction executing unit of the processor is able to independently access said first portion and said second portion of said register.  
 
     
     
       13. An image processing device comprising:
 a processor which includes an instruction decoder for decoding instructions of an image processing program and an instruction executing unit for executing the instructions responsive to outputs from said instruction decoder, and outputs the execution result by said instruction executing unit; and  
 a data loader, connected to said processor, which outputs image data for fixed length codes to said processor,  
 wherein said processor is configured to perform a process of decoding a first kind of image data of variable length codes to a second kind of image data of fixed length codes, a process of transforming the second kind of image data to a third kind of image data, and a process of a prescribed operation between the third kind of image data and the image data of fixed length codes output from said data loader,  
 and wherein the processor includes a register having a first portion and a second portion for storing two image data each comprising a number (n) of bits, and the instruction executing unit of the processor is able to independently access said first portion and said second portion of said register.  
 
     
     
       14. An image processing device comprising:
 a processor which includes an instruction decoder for decoding instructions of an image processing program and an instruction executing unit for  for executing the instructions responsive to outputs for  from said instruction decoder, and outputs the execution result by said instruction executing unit; and  
 a variable length code decoder, connected to said processor, which decodes a first kind of image data of variable length codes to a second kind of image data of fixed length codes, and outputs the second kind of data to said processor,  
 wherein said processor is configured to perform a process of transforming the second kind of image data output from said variable length code decoder to a third kind of image data according to the image processing program,  
 and wherein each of the instructions decoded by the instruction decoder of the processor includes a first operation specifying field and a second operation speci- fying field each for specifying an operation, and the instruction executing unit of the processor has a first operation unit and a second operation unit for perform- ing said operations specified by said first and second operation specifying fields in parallel.  
 
     
     
       15. An image processing device comprising:
 a processor which includes an instruction decoder for decoding instructions of an image processing program and an instruction executing unit for executing the instructions responsive to outputs from said instruction decoder, and outputs the execution result by said instruction executing unit; and  
 a data loader, connected to said processor, which outputs image data for fixed length codes to said processor,  
 wherein said processor is configured to perform a process of decoding a first kind of image data of variable length codes to a second kind of image data of fixed length codes, a process of transforming the second kind of image data to a third kind of image data, and a process of a prescribed operation between the third kind of image data and the image data of fixed length codes output from said data loader, and  
 wherein each of the instructions decoded by the instruc- tion decoder of the processor includes a first operation specifying field and a second operation specifying field each for specifying an operation, and the instruction executing unit of the processor has a first operation unit and a second operation unit for performing said opera- tions specified by said first and second operation speci- fying fields in parallel.  
 
     
     
       16. An image processing device comprising:
   a processor, connected to a memory, which includes an instruction decoder for decoding instructions of an image processing program and an instruction executing unit for executing the instructions responsive to outputs from said instruction decoder, and outputs the execution result by said instruction executing unit; and        a variable length code decoder, connected to the memory, which decodes a first kind of image data of variable length codes to a second kind of image data of fixed length codes, and provides the second kind of image data to the memory,        wherein said processor is configured to perform a process of reading the second kind of image data from the memory and transforming the second kind of image data a to a third kind of image data according to the image processing program, and        wherein the instructions decoded by the instruction decoder of the processor includes at least an instruction having a first operation specifying field and a second operation specifying field each for specifying an operation, and the instruction executing unit of the processor has a first operation unit and a second operation unit for performing said operations specified by said first and second operation specifying fields in parallel.     
     
     
       17. The image processor device as set forth in  claim 14 , further comprising
   a data loader loading data from a memory and outputting image data of fixed length codes;        wherein said processor is configured to further perform a process of operating between the third kind of image data and the image data of fixed length codes output from the data loader.     
     
     
       18. The image processor device as set forth in  claim 16 , further comprising:
   a data loader loading data from another memory and outputting image data of fixed length codes; wherein said processor is configured to further perform a process of operating between the third kind of image data and the image data of fixed length codes output from the data loader.     
     
     
       19. An image processing device comprising:
   a processor, connected to a memory, which includes an instruction decoder for decoding instructions of an image processing program and an instruction executing unit for executing the instructions responsive to outputs from said instruction decoder, and outputs the execution result by said instruction executing unit; and        a data loader, connected to the memory, which outputs image data for fixed length data to the memory,        wherein said processor is configured to perform a process of decoding a first kind of image data of variable length codes to a second kind of image data, of fixed length scodes, a process of transforming the second kind of image data to a third kind of image data and a process of a prescribed operation between the third kind of image data and the image data of fixed length codes output from the memory, and      wherein each of the instructions decoded by the instruction decoder of the processor includes a first operation specifying field and a second operation specifying field each for specifying an operation, and the instruction executing unit of the processor has a first operation unit and a second operation unit for the processor for performing said operations specified by said first and second operation specifying fields in parallel.     
     
     
       20. An image processing device comprising:
   a processor which includes an instruction decoder for decoding instructions of an image processing program and an instruction executing unit for executing the instructions responsive to outputs from said instruction decoder; and        a variable length code decoder, which decodes a first kind of image data of variable length codes to a second kind of image data of fixed length codes, and outputs the second kind of data,        wherein said processor is configured to perform a process of transforming the second kind of image data output from said variable length code decoder to a third kind of image data according to the image processing program, and        wherein the processor further includes a plurality of registers storing image data, each register having a plurality of portions, said instruction executing unit executes a prescribed instruction decoded by said instruction decoder, the prescribed instruction having a first field specifying contents of an operation, a second field specifying a register number of each of said plurality of registers, and a third field specifying each of the plurality of portions, said instruction executing unit performing the operation specified by the first field using a portion specified by the third field in a register specified by the second field.     
     
     
       21. The image processing device as set forth in  claim 20 , wherein
   said variable length code decoder outputs the second kind of image data to a memory, and said processor receives the second kind of image data from the memory.     
     
     
       22. An image processing device comprising:
   a processor which includes an instruction decoder for decoding instructions of an image processing program and an instruction executing unit for executing the instructions responsive to outputs from said instruction decoder; and        a data loader, which outputs image data for fixed length codes,        wherein said processor is configured to perform a process of decoding a first kind of image data variable length codes to a second kind of image data of fixed length codes, a process of transforming the second kind of image data to a third kind of image data, and a process of prescribed operation between the third kind of image data and the image data of fixed length codes output from said data loader, and        wherein the processor further includes a plurality of registers storing image data, each register having a plurality of portions, said instruction executing unit executes a prescribed instruction decoded by said instruction decoder, the prescribed instruction having a first field specifying contents of an operation, a second field specifying a register number of each of said plurality of registers and a third field specifying each of the plurality of portions, said instruction executing unit performing the operation specified by the first field using a portion specified by the third field in a register specified by the second field.     
     
     
       23. The image processing device as set forth in  claim 22 , wherein
   said data loader outputs the image data of fixed length codes to a memory, and said processor receives the image data of fixed length codes from the memory.