USRE39211EExpiredUtility

Method for manufacturing a liquid crystal display

Assignee: SAMSUNG ELECTRONICS CO LTDPriority: Dec 28, 1995Filed: Jul 7, 2003Granted: Aug 1, 2006
Est. expiryDec 28, 2015(expired)· nominal 20-yr term from priority
H10D 86/441H10D 86/0231H10D 86/60H10D 86/00H10D 30/6739H10D 30/0321H10D 30/0316G02F 1/1345G02F 1/1362G02F 1/13458G02F 1/13439
56
PatentIndex Score
8
Cited by
50
References
37
Claims

Abstract

A method for manufacturing a liquid crystal display which reduces the number of photolithography processes is provided. The method includes the steps of forming a gate electrode and a gate pad by depositing a first metal film and a second metal film on a substrate of a TFT area and a gate-pad connecting area, respectively, in the described order, by a first photolithography process, forming an insulation film on the entire surface of the substrate on which the gate electrode and the gate pad are formed, forming a semiconductor film pattern on the insulating film of the TFT area by a second photolithography process, forming a source electrode/drain electrode and pad electrode composed of a third metal film using a third photolithography process in the TFT portion and pad portion, respectively, forming a passivation film pattern which exposes a portion of the drain electrode, a portion of the gate pad, and a portion of the pad electrode by a fourth photolithography process, exposing the first metal film by etching the second metal film which constitutes the gate pad using the passivation film pattern as a mask, and forming a pixel electrode connected to the drain electrode of the TFT area for connecting the gate pad of the gate-pad connecting area to the pad electrode of the pad area using a fifth photolithography process. Therefore, it is possible to reduce the number of photolithography processes, to improve the manufacturing yield, and to suppress growth of a hillock of an Al film.

Claims

exact text as granted — not AI-modified
1. A method for manufacturing a liquid crystal display, comprising the steps of:
 forming a gate electrode and a gate pad by depositing a first metal film and a second metal film over a substrate in a TFT area and a gate-pad connecting area, respectively, by a first photolithography process;    forming an insulating film over the gate electrode and the gate pad;    forming a semiconductor film pattern over the insulating film in the TFT area by a second photolithography process;    forming a source electrode/drain electrode and pad electrode in the TFT portion and pad portion, respectively, using a third photolithography process, the source electrode/drain electrode and pad electrode all being comprised of a third metal film;    forming a passivation film pattern by a fourth photolithography process, the passivation film exposing a portion of the drain electrode, a portion of the gate pad, and a portion of the pad electrode;    exposing the first metal film by etching a portion of the second metal film that comprises the gate pad using the passivation film pattern as a mask; and    forming a pixel electrode connected to the drain electrode of the TFT area by a fifth photolithography process, the pixel electrode acting to connect the gate pad of the gate-pad connecting area to the pad electrode of the pad area.    
     
     
       2. A method for manufacturing a liquid crystal display as recited in  claim 1 , wherein the first metal film comprises a refractory metal. 
     
     
       3. A method for manufacturing a liquid crystal display as recited in  claim 1 , wherein the second metal film comprises Al or an Al-alloy. 
     
     
       4. A method for manufacturing a liquid crystal display as recited in  claim 2 , wherein the first metal film comprises a material selected from the group consisting of Cr, Ta, Mo, and Ti. 
     
     
       5. A method for manufacturing a liquid crystal display as recited in  claim 1 , wherein the third metal film comprises a material selected from the group consisting of Cr, Ta, Mo, and Ti. 
     
     
       6. A method for manufacturing a liquid crystal display as recited in  claim 1 , wherein taper-etching is performed on the second metal film in the first photolithography process and then etching of the first metal film is performed. 
     
     
       7. A method for manufacturing a liquid crystal display as recited in  claim 1 , wherein the first metal film is wider than the second metal film. 
     
     
       8. A method for manufacturing a liquid crystal display, comprising the steps of:
 forming a gate electrode and a gate pad by depositing a first metal film and a second metal film over a substrate of a TFT area and a pad area, respectively, by a first photolithography process;    forming an insulating film over the gate electrode and the gate pad;    forming a semiconductor film pattern over the insulating film in the TFT area by a second photolithography process;    forming a source electrode and a drain electrode in the TFT area by a third photolithography process, the source electrode and the drain electrode comprising a third metal film;    forming a passivation film pattern that exposes a portion of the drain electrode of the TFT area and a portion of the gate pad of the pad area by forming a passivation film over the source electrode and the drain electrode and performing a fourth photolithography process on the passivation film and the insulating film;    exposing the first metal film of the pad area by etching the second metal film using the passivation film pattern as a mask; and    forming a pixel electrode that is connected to the drain electrode of the TFT area and contacts the first metal film of the pad area by a fifth photolithography process.    
     
     
       9. A method for manufacturing a liquid crystal display as recited in  claim 8 , wherein the first metal film comprises a refractory metal. 
     
     
       10. A method for manufacturing a liquid crystal display as recited in  claim 8 , wherein the second metal film comprises Al or an Al-alloy. 
     
     
       11. A method for manufacturing a liquid crystal display as recited in  claim 9 , wherein the first metal film comprises a material selected from the group consisting of Cr, Ta, Mo, and Ti. 
     
     
       12. A method for manufacturing a liquid crystal display as recited in  claim 8 , wherein the third metal film comprises a material selected from the group consisting of Cr, Ta, Mo, and Ti. 
     
     
       13. A method for manufacturing a liquid crystal display as recited in  claim 8 , wherein taper-etching is performed on the second metal film in the first photolithography process and then etching the first metal film is performed. 
     
     
       14. A method for manufacturing a liquid crystal display as recited in  claim 8 , wherein the insulating film comprises a nitride film SiN x . 
     
     
       15. A method for manufacturing a liquid crystal display as recited in  claim 8 , wherein the insulating film comprises a double film including a nitride film SiN x  and an oxide film SiO x . 
     
     
       16. A TFT substrate, comprising:
   a gate electrode comprising a first metal film over a substrate and a second metal film over the first metal film;        a gate pad consisting the first metal film and a portion of a removed area of the second metal film;        an insulated film over the gate electrode and having an exposed area of the first metal film over the gate pad;        a semiconductor film pattern over the insulated film;        a source electrode formed over a first portion of the semiconductor film pattern;        a drain electrode formed over a second portion of the semiconductor film pattern;        a passivation film pattern formed over the source electrode, having a contact hole over the drain electrode and having an exposed area of the first metal film of the gate pad;        a first pixel electrode pattern electrically contacted to the drain electrode on the passivation film pattern; and        a second pixel electrode pattern electrically contacted to the exposed area of the first metal film of the gate pad.     
     
     
       17. A TFT substrate, as recited in  claim 16 , wherein the first metal film comprises a refractory metal. 
     
     
       18. A TFT substrate, as recited in  claim 17 , wherein the first metal film comprises a material selected from the group consisting of CR, Ta, Mo, and Ti. 
     
     
       19. A TFT substrate, as recited in  claim 16 , wherein the second metal film comprises Al or an Al alloy. 
     
     
       20. A TFT substrate, as recited in  claim 16 , wherein the insulated film comprises a nitride film SiN. 
     
     
       21. A TFT substrate, as recited in  claim 16 , wherein the first and second pixel patterns comprise ITO. 
     
     
       22. A TFT substrate, as recited in  claim 16 , wherein a portion of the passivation film directly contacts the semiconductor film pattern. 
     
     
       23. A TFT substrate, as recited in  claim 16 , wherein a portion of the passivation film directly contacts the semiconductor film pattern. 
     
     
       24. A TFT substrate as in  claim 16 , wherein at least one of the first and the second metal film of the gate electrode and the gate pad has tapered- sidewalls.   
     
     
       25. A TFT substrate as in  claim 24 , wherein the second metal film has tapered sidewalls. 
     
     
       26. A TFT substrate as in  claim 16 , wherein the semiconductor film pattern comprises:
   an amorphous silicon film on the insulated film; and        a doped amorphous silicon film on the amorphous silicon film.     
     
     
       27. A TFT substrate as in  claim 16 , wherein the second pixel electrode pattern contacts portions of the exposed gate pad. 
     
     
       28. A TFT substrate, comprising:
   a gate electrode comprising at least a refractory metal film formed over a first portion of a substrate;        a gate pad comprising the refractory metal film formed on a second portion of a substrate;        an insulated film formed over the gate electrode and having an exposed area corresponding to the refractory metal film of the gate pad;        a semiconductor film pattern formed over the insulated film;        a source electrode formed over a first portion of the semiconductor film pattern;        a drain electrode formed over a second portion of the semiconductor film pattern;        a passivation film pattern formed over the source electrode, having a contact hole over the drain electrode and having an exposed area corresponding to the refractory metal film of the gate pad;        a first pixel electrode pattern electrically contacted to the drain electrode on the passivation film pattern; and        a second pixel electrode electrically contacted to the exposed area of the refractory metal film of the gate pad.     
     
     
       29. A TFT substrate, as recited in  claim 28 , wherein the refractory metal film comprises a material selected from the group consisting of Cr, Ta, Mo, and Ti. 
     
     
       30. A TFT substrate, as recited in  claim 28 , further comprising a second metal film formed on the refractory metal film over the first portion of the substrate, and formed on the refractory metal film of the gate pad except for the exposed area thereof. 
     
     
       31. A TFT substrate, as recited in  claim 28 , wherein the second metal film comprises Al or Al alloy. 
     
     
       32. A TFT substrate, as recited in  claim 28 , wherein the insulated film comprises a nitride film SiN. 
     
     
       33. A TFT substrate, as recited in  claim 28 , wherein the first and second pixel patterns comprise ITO. 
     
     
       34. A TFT substrate as in  claim 28 , wherein at least one of the first and the second metal film of the gate electrode and the gate pad has tapered- sidewalls.   
     
     
       35. A TFT substrate as in  claim 34 , wherein the second metal film has tapered sidewalls. 
     
     
       36. A TFT substrate as in  claim 28 , wherein the semiconductor film pattern comprises:
   an amorphous silicon film on the insulated film; and        a doped amorphous silicon film on the amorphous silicon film.     
     
     
       37. A TFT substrate as recite in  claim 28 , wherein the second pixel electrode pattern contacts portions of the exposed gate pad.

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