Image motion compensating address generator

Abstract

An image motion compensating address generator is disclosed including a mode selector for selecting a field mode or frame mode according to a video mode signal and a slice position signal, an address selection controller for controlling the generation of addresses according to the video mode signal and a motion coding type signal, a Y-direction read address generator for producing a Y-direction read address in units of processed block, an X-direction read address generator for dividing the processed block into four phases in the X-direction and generating an X-direction read address, an X-direction write address generator for delaying the processed-block position signal and a field processed-block clock signal, and generating the X-direction write address of four phases, a Y-direction write address generator for producing a Y-direction write address, and a read & write controller for selecting outputting the X-direction and Y-direction read and write addresses according to a read/write selection toggle signal and an X-direction motion vector signal.

1. An image motion compensating address generator for a generating addresses of a memory, comprising:
 mode selector means for selecting a field mode or frame mode according to a video mode signal indicative of whether an input video signal is a frame unit or field unit and a slice position signal indicative of the position of a slice, to thereby control the video signal to be processed;  
 address selection controller means for controlling the generation of the addresses according to the video mode signal and a motion coding type signal indicative of the video processing mode of a block to be processed;  
 Y-direction read address generator means for producing a Y-direction read addressthe addresses in units of processed block by using the signal output from the mode selector means according toand the address selection controller means, a Y-direction motion vector signal, and a vertical field selection signal;  
 X-direction read address generator means for dividing the processed block into four phases in the X direction and generating an X-direction read address by using a processed-block position signal indicative of the position of the processed block and an X-direction motion vector signal according to the address selection controller means;  
 X-direction write address generator means for delaying the processed-block position signal and a field processed-block clock signal, and generating the X-direction write address of four phases, to thereby write read-out video data;  
 Y-direction write address generator means for producing a Y-direction write address by using the signal output from of the mode selector means according to the address selection controller means and the X-direction write address generator means, to thereby write read-out video data ; and  
 read & write controller means for selectively outputting the X-direction and Y-direction read and write addresses according to a read/write selection toggle signal and an X-directiona motion vector signal among the X-direction and Y-direction read and write addresses output from the Y-direction read address generator means, X-direction read address generator means, X-direction write address generator means and Y-direction write address generator means .  
 
     
     
       2. An The image motion compensating address generator as claimed in  claim 1 , wherein the mode selector means comprises:
 a video mode selector for determining whether an address is generated in a field mode or frame mode according to the video mode signal; and  
 a field/frame mode processor for establishing the position of the slice in the field mode and frame mode according to the signal output from the video mode selector means and the slice position signal.  
 
     
     
       3. An The image motion compensating address generator as claimed in  claim 2 , wherein the video mode selector comprises a NAND gate for NAND-operating the video mode signal and outputting it to the field/frame mode processor. 
     
     
       4. An The image motion compensating address generator as claimed in  claim 2 , wherein the field/frame mode processor comprises a multiplexer for selecting one of the slice position signal and a signal double the slice position signal according to the signal output from a NAND gate of the video mode selector. 
     
     
       5. An The image motion compensating address generator as claimed in  claim 1 , wherein the address selection controller means comprises:
 a control signal generator for receiving the video mode signal and the motion coding type signal, and outputting a processing selection control signal for controlling the selection of modes and another a control signal to the Y-direction read address generator means, X-direction read address generator means and Y-direction write address generator means ;  
 a first delay for delaying a frame processed-block clock signal for processing the processed-block in frames in order for synchronization with the processing selection control signal and control signal output from the control signal generator;  
 a second delay for delaying a field processed-block clock signal for processing the processed-block in fields in order for synchronization with the processing selection control signal and control signal output from the control signal generator;  
 a multiplexer for selecting one of the signals output from the first and second delays according to the delay signal of the control signal generator;  
 a counter for counting to preset the X-direction read an address according to an input main clock;  
 a third delay for delaying the signal output from the multiplexer  24  in order for synchronization with the signal output from the counter; and  
 an AND gate for AND-operating the signal output from the third delay and the signal output from the counter and outputting a preset signal for presetting the X-direction read address.  
 
     
     
       6. An The image motion compensating address generator as claimed in  claim 5 , wherein the control signal generator comprises:
 an AND gate for AND-operating the video mode signal;  
 an exclusive-OR gate for EXCLUSIVE-OR-operating the signal output from the AND gate and the motion coding type signal to thereby control the multiplexer; and  
 a NAND gate for NAND-operating the video mode signal and the motion coding type signal and outputting a processing selection control signal.  
 
     
     
       7. An The image motion compensating address generator as claimed in  claim 5 , wherein the counter varies the period of presetting the X-direction read address by using a clear port in case that a half pel is used. 
     
     
       8. An The image motion compensating address generator as claimed in claim  1   29 , wherein the Y-direction first read address generator means comprises:
 a Y-direction read address starting point operator for operating the Y-direction a first starting point of a processed block to be read, according to the signal output from the field/frame mode processor of the mode selector means and a Y-direction the first direction motion vector signal;  
 a processed-block unit Y-direction read address generator for generating Y-direction the first direction read addresses of several modes so that the signal output from the Y-direction read address starting point operator coincides with the processed block; and  
 a video mode & and motion coding type processing selector for receiving a signal output from the processed-block unit Y-direction read address generator and a vertical the first field selection signal according to the address selection controller means, to thereby outputting a Y-direction the first direction read address fit for the respective modes.  
 
     
     
       9. An The image motion compensating address generator as claimed in  claim 8 , wherein the Y-direction read address starting point operator comprises:
 first, second and third serially coupled adders for multiplying the Y-direction a first direction size of the processed block to the signal output from the field/frame mode processor of the mode selector means and adding a Y-direction the first direction motion vector signal; and  
 a latch for stabilizing the signals output from the first, second and third adders.  
 
     
     
       10. An The image motion compensating address generator as claimed in  claim 8 , wherein the processed-block unit Y-direction read address generator comprises:
 a first counter for receiving the signal output from the latch of the Y-direction read address starting point operator and counting to generate the Y-direction first direction read address fit for the frame mode; and  
 a second counter for shifting the signal output from the latch of the Y-direction read address starting point operator, and counting to generate the Y-direction first direction read address fit for the field mode.  
 
     
     
       11. An The image motion compensating address generator as claimed in  claim 8 , wherein the video mode & and motion coding type processing selector comprises:
 a multiplexer for selecting the Y-direction first direction read address of one mode of frame-mode Y-direction first direction read address and field-mode Y-direction first direction read address output from the processed-block unit Y-direction read address generator according to the address selection controller means, and if the field-mode Y-direction first direction read address is selected, including a vertical the first field selection signal into one bit of the lower level; and  
 a latch for stabilizing the signal output from the multiplexer.  
 
     
     
       12. An The image motion compensating address generator as claimed in claim  1   30 , wherein the X-direction second read address generator means comprises:
 an X-directiona read address starting point operator for operating the X-directiona second direction starting point of the processed block to read by using athe processed-block position signal and an X-directionthe second direction motion vector signal; and  
 a processed-block unit X-direction read address generator for receiving the signal output from the X-direction read address starting point operator according to the address selection controller means, dividing the processed block into four phases and generating the X-direction second direction read address.  
 
     
     
       13. An The image motion compensating address generator as claimed in  claim 12 , wherein the X-direction read address starting point operator comprises:
 a first latch for latching the processed-block position signal for the purpose of synchronization;  
 a second latch for latching the X-direction second direction motion vector signal for the purpose of synchronization;  
 first, second and third serially coupled adders for multiplying the X-direction a second direction size of the processed block unit to the signal output from the first latch and adding the signal output from the second latch; and  
 a third latch for stabilizing the signal output from the first, second, and third adders.  
 
     
     
       14. An The image motion compensating address generator as claimed in  claim 12 , wherein the processed-block unit X-direction read address generator comprises:
 a counter for receiving the signal output from the third latch of the X-direction read address starting point operator, being preset according to a preset signal output from the address selection controller means, dividing the processed block in four phases in the X direction second direction and counting to generate the X-direction second direction read address; and  
 a latch for stabilizing the signal output from the counter.  
 
     
     
       15. An The image motion compensating address generator as claimed in  claim 14 , wherein the counter is preset for a period in which a value in which the processed block is divided into four phases in the X direction second direction, is added by one in case of half pel. 
     
     
       16. An image motion compensating address generator as claimed in claim  1   30 , wherein the X-direction second write address generator means comprises:
 an X-directiona write address delay controller for delaying the processed-block position signal and field processed-block clock signal for a predetermined time so as to rewrite read-out video data ; and  
 an X-directiona write address generator for dividing the processed block into four phases and generating the X-directionsecond direction write address by using the signal output from the X-direction write address delay controller.  
 
     
     
       17. An The image motion compensating address generator as claimed in  claim 16 , wherein the X-direction write address delay controller comprises:
 a first D flipflop for receiving a frame processed-block clock signal for processing the processed block in frames and outputting a clock signal;  
 a latch portion having a plurality of serially coupled latches for receiving the signal output from the first D flipflop as a clock input and delaying the processed block clock signal for processing the processed block in fields and the processed-block position signal for a predetermined time;  
 a first counter for receiving a main clock signal and performing counting;  
 a D flipflop portion having a plurality of serially coupled flipflops for receiving the signal output from the first counter as a clock input and delaying the field processed-block clock signal delayed and output from the latch portion for a predetermined time;  
 a second D flipflop for receiving the main clock signal as a clock input and receiving the field processed-block clock signal delayed and output from the D flipflop portion as data input;  
 an EXCLUSIVE-NOR gate for EXCLUSIVE-NOR-operating the data input signal and output signal of the second D flipflop; and  
 a third D flipflop for receiving the signal output from the EXCLUSIVE-NOR gate as data input and receiving the main clock signal as the clock input.  
 
     
     
       18. An The image motion compensating address generator as claimed in  claim 16 , wherein the X-direction write address generator comprises:
 a second counter for counting only two bits by taking the signal output from the third D flipflop of the X-direction write address delay controller as the reset signal;  
 a latch for temporarily storing and stabilizing the processed-block position signal delayed and output from the latch portion; and  
 a delay for delaying the signal output from the second counter for the purpose of synchronization.  
 
     
     
       19. An image motion compensating address generator as claimed in claim  1   30 , wherein the Y-direction first write address generator means comprises:
 a Y-direction write address generator for generating a Y-direction the first direction write address in units of processed block by using the signal output from a field/frame mode processor of the mode selector means according to an X-direction write address delay controller of the X-direction write address generator means and the delayed processed- block position signal ; and  
 a video mode & and motion coding type processing selector for selectively outputting the Y-direction first direction write address fit for the respective modes among the signals output from the Y-direction write address generator according to the address selection controller means.  
 
     
     
       20. An image motion compensating address generator as claimed in claim  19   21 , wherein the video mode & and motion coding type processing selector comprises:
 a multiplexer for selecting one of the output signal of the counter and the shifted output signal of the counter according to the address selection controller means; and  
 a latch for stabilizing the signal output from the multiplexer.  
 
     
     
       21. An The image motion compensating address generator as claimed in  claim 19 , wherein the Y-direction write address generator comprises:
 a counter preset according to the signal output from the X-direction write address delay controller delayed processed- block position signal  and for multiplying the Y-direction first direction size of the processed-block unit to the signal output from the field/frame mode processor of the mode selector means, and counting periodically according to the main clock signal.  
 
     
     
       22. An The image motion compensating address generator as claimed in  claim 21 , wherein the counter counts whenever the X-direction second direction write addresses divided into four phases by the main clock are all generated and preset. 
     
     
       23. An The image motion compensating address generator as claimed in  claim 22 , wherein the counter uses only the higher bits of an output signal excluding the two bits of the lower level, not using the two bits of the lower level. 
     
     
       24. An The image motion compensating address generator as claimed in claim  1   30 , wherein the read & write controller means comprises:
 a Y-direction read & write first selector for selectively outputting one of the Y-direction first direction read address and Y-direction first direction write address output from the Y-direction first read address generator means and Y-direction first write address generator means according to the read/write selection toggle signal;  
 a four-phase address generator for compensating for the X-direction second direction read address output from the X-direction second read address generator means according to the read/write selection toggle signal; and  
 an X-direction read & writea second selector for selecting one of the X-directionsecond direction read address and X-directionsecond direction write address output from the four-phase address generator and X-directionsecond write address generator means and dividely outputting the selected address in four phases according to the read/write selection toggle signal.  
 
     
     
       25. An The image motion compensating address generator as claimed in  claim 24 , wherein the X-direction read & write second selector comprises:
 first, second, third and fourth multiplexers for selecting one of the X-direction second direction read address and X-direction second direction write address output from the four-phase address generator and X-direction second write address generator means according to the read/write selection toggle signal; and  
 first, second, third and fourth latches for stabilizing the X-direction second direction read address and X-direction second direction write address output from the first, second, third and fourth multiplexers.  
 
     
     
       26. An image motion compensating address generator as claimed in  claim 24 , wherein the Y-direction read & write first selector comprises:
 a multiplexer for selecting one of the Y-direction first direction read address and Y-direction first direction write address output from the Y-direction first read address generator means and Y-direction first write address generator means according to the read/write selection toggle signal; and  
 a latch for stabilizing the Y-direction first direction read address and Y-direction first direction write address output from the multiplexer.  
 
     
     
       27. An image motion compensating address generator as claimed in  claim 24 , wherein the four-phase address generator comprises:
 a compensation controller for controlling the compensation of the X-direction second direction read address divided into four phases by using the read/write selection toggle signal and two bit signals of the lower level of the X-direction second direction motion vector signal of the backward and forward frames;  
 first, second and third latches for latching the X-direction second direction read address output from the processed-block unit X-direction read address generator of the X-direction second read address generator means according to the compensation controller; and  
 a fourth latch for latching the X-direction second direction read address output from the processed-block unit X-direction read address generator of the X-direction second direction read address generator means according to al ow-level signal.  
 
     
     
       28. An The image motion compensating address generator as claimed in  claim 27 , wherein the compensation controller comprises:
 a first multiplexer for selecting one of the lowest bit signals of the X-direction second direction motion vector signal of the backward and forward frames according to the read/write selection toggle signal;  
 a second multiplexer for selecting one of the second lowest bit signals of the X-direction second direction motion vector signal of the backward and forward frames according to the read/write selection toggle signal;  
 an OR gate for OR-operating the signals output from the first and second multiplexers and outputting a signal for controlling the first latch;  
 a buffer for delaying the signal output from the second multiplexer and outputting a signal for controlling the second latch; and  
 an AND gate for OR-operating the signals output from the first and second multiplexers and outputting a signal for controlling the third latch.  
 
     
     
       29. The image motion compensating address generator as claimed in  claim 1 , wherein said address generator means comprises:
   a first read address generator means for producing a first direction read address in units of the processed block by using the signal output from the mode selector means according to the address selection controller means, a first direction motion vector signal, and a first field selection signal; and        a first write address generator means for producing a first direction write address by using the signal output from of the mode selector means according to the address selection controller means.     
     
     
       30. The image motion compensating address generator as claimed in  claim 29 , wherein said address generator means further comprises:
   a second read address generator means for dividing the processed block into four phases in a second direction and generating a second direction read address by using a processed - block position signal indicative of the position of the processed block and a second direction motion vector signal and coupled to the address selection controller means; and        a second write address generator means for delaying the processed - block position signal, which is provided to said first write address generator means, and a field processed - block clock signal, and generating a second direction write address of four phases.     
     
     
       31. A controller for an image motion compensating address generator to generate addresses of a memory, comprising:
   a selector that selects one of a field unit and a frame unit according to a video mode signal indicative of whether an input video signal is one of a frame unit and a field unit and a slice position signal indicative of a position of a slice; and        an address controller that controls a generation of addresses according to the video mode signal and a motion coding signal indicative of the video processing mode.     
     
     
       32. The controller of  claim 31 , wherein the video mode signal comprises first and second bits and each bit has a binary value, the video mode signal being indicative of the frame unit when the first and second bits have a same binary value and the video mode signal being indicative of the field unit when the first and second bits have different binary values. 
     
     
       33. The controller of  claim 32 , wherein the first and second bits have binary values of “ 1 ” and “ 1 ”, respectively, for the frame unit. 
     
     
       34. The controller of  claim 32 , wherein the first and second bits have one of binary values of “ 1 ” and “ 0 ” and binary values of “ 0 ” and “ 1 ” for the field unit. 
     
     
       35. The controller of  claim 34 , wherein the binary values of “ 1 ” and “ 0 ” are indicative of a lower field during the field unit, and the binary values of “ 0 ” and “ 1 ” are indicative of an upper field during the field unit. 
     
     
       36. The controller of  claim 32 , wherein the motion coding type signal is indicative of field base mode or frame base mode when the first and second bits are indicative of the frame unit, or is indicative of field base mode or N- by - M base mode when the first and second bits are indicative of the field unit, where N and M are integers greater than zero.   
     
     
       37. The controller of  claim 36 , wherein N and M are  16  and  8 , respectively. 
     
     
       38. The controller of  claim 36 , wherein during the frame unit, the motion coding type signal has a value of “ 01 ” for the field base mode and a value of “ 10 ” for the frame base mode. 
     
     
       39. The controller of  claim 35 , wherein during the field unit, the motion coding type signal has a value of “ 01 ” for the field base mode, and the motion coding type signal has a value of “ 10 ” for the N- by - M base mode.   
     
     
       40. The controller of  claim 31 , wherein said selector comprises:
   a logic gate for performing a first logical operation on the video mode signal; and        a multiplexer coupled for receiving an output of said logic gate and the slice position signal and outputting a prescribed multiple of the slice position signal based on whether the output of said logic gate indicates one of field unit and frame unit.     
     
     
       41. The controller of  claim 40 , wherein the slice position signal is provided as the output when the output of said logic gates indicates the frame unit, and the prescribed multiple is two when the output of said logic gate indicates the field unit. 
     
     
       42. The controller of  claim 36 , wherein said address controller comprises:
   a control circuit coupled for receiving the video mode signal and motion coding type signal such that said control signal outputs  (   1   )  a first control signal indicative of the field base mode during the frame unit, the frame base mode during the frame unit, field base mode during the field unit, or N - by - M base mode during the field unit, and  (   2   )  a second control signal for controlling the image motion compensating address generator;        a multiplexer coupled for receiving a first clock signal for synchronization during the frame unit and a second clock signal for synchronization during the frame unit, said multiplexer being responsive to the first control signal to output one of the first clock signal and the second clock signal;        a counter for counting a main clock signal to reset the addresses when a count value reaches a prescribed value; and        a first logic gate coupled for receiving the output of said counter and the output of said multiplexer and performing a first logical operation to output a preset signal which presets the addresses for a predetermined period of time.     
     
     
       43. The controller of  claim 42 , wherein said address controller further comprises:
   a first delay for delaying the first clock signal prior to input to said multiplexer;        a second delay for delaying the second clock signal prior to input to said multiplexer; and        a third delay for delaying the output of the multiplexer prior to input to said first logic gate.     
     
     
       44. The controller of  claim 42 , wherein said control circuit comprises:
   a second logic gate for receiving the video mode signal;        a third logic gate for receiving the video mode signal and the mode coding type signal and providing the second control signal; and        a fourth logic gate receiving an output of said second logic gate and the motion coding type signal, and providing the first control signal.     
     
     
       45. The controller of  claim 44 , wherein said first, second and third logic gates are AND gates and said fourth logic gate is an exclusive OR gate. 
     
     
       46. An image motion compensating address generator for generating addresses of a memory, comprising:
   a selector that selects one of a field unit and a frame unit according to a video mode signal and a slice position signal indicative of a position of a slice;        an address controller that controls a generation of addresses according to the video mode signal and a motion coding signal indicative of the video processing mode;        an address generator responsive to outputs of said mode selector and said address controller, first and second motion vector signals and a field selection signal to generate the addresses; and        a controller for selectively outputting the addresses based on an operational mode for the memory and the second motion vector signal.     
     
     
       47. The image motion compensating address generator of  claim 46 , wherein the video mode signal comprises first and second bits and each bit has a binary value, the video mode signal being indicative of the frame unit when the first and second bits have a same binary value and the video mode signal being indicative of the field unit when the first and second bits have different binary values. 
     
     
       48. The image motion compensating address generator of  claim 47 , wherein the motion coding type signal is indicative of field base mode or frame base mode when the first and second bits are indicative of the frame unit, or is indicative of field base mode or N- by - M base mode when the first and second bits are indicative of the field unit, where N and M are integers greater than zero.   
     
     
       49. The image motion compensating address generator of  claim 46 , wherein said selector comprises:
   a video mode selector selects one of the frame unit and the field unit based on the video mode signal; and        a mode processor coupled for receiving an output of said video mode selector and the slice position signal and outputting a prescribed multiple of the slice position signal based on whether the output of said video mode selector indicates one of field unit and frame unit.     
     
     
       50. The image motion compensating address generator of  claim 49 , wherein the slice position signal is provided as the output of said mode processor when the output of said video mode selector indicates the frame unit, and the prescribed multiple is two when the output of said video mode selector indicates the field unit. 
     
     
       51. The image motion compensating address generator of  claim 46 , wherein said address generator comprises:
   a first read and write address generator coupled to said selector and said address selection controller and responsive to the first motion vector signal to generate one of first read address and first write address; and        a second read and write address generator coupled to said first read and write address generator and responsive to the second motion vector signal and a processed block position signal to generate one of second read address and second write address.     
     
     
       52. The image motion compensating address generator of  claim 51 , wherein said controller comprises:
   a first selector coupled to said first read and write address generator for providing one of the first read address and first write address when the operational mode of the memory is one of a read operation and a write operation, respectively;        a phase generator coupled to said second read and write address generator for dividing the second read address into a plurality of phases based on the second motion vector signal and the operational mode; and        a second selector coupled to said second read and write address generator and said phase generator and providing one of the second write address and the second read address of different phases when the operational mode of the memory is one of a read operation and a write operation, respectively.     
     
     
       53. The image motion compensating address generator of  claim 51 , wherein said first read and write address generator comprises:
   a Y - direction read address generator coupled to said selector and address controller and responsive to the first motion vector signal to generate a Y - direction read address; and        a Y - direction write address generator coupled to said Y - direction read address generator, said selector and said second read and write address generator to generate a Y - direction write address.     
     
     
       54. The image motion compensating address generator of  claim 51 , wherein said second read and write address generator comprises:
   an X - direction read address generator coupled to said address controller and responsive to the second motion vector signal and a processed - block position signal to generate an X - direction read address; and        an X - direction write address generator coupled to said first read and write address generator and responsive to the processed block position signal to generate an X - direction write address.     
     
     
       55. The image motion compensating address generator as claimed in  claim 29 , wherein the first direction is a Y- direction, and the second direction is an X - direction.