Sense amplifier circuit

Abstract

In order to enhance the sensitivity of a sense amplifier circuit, each one of the transistor pair composing the sense amplifier circuit is formed by transistors connected parallel in an even number of stages, and therefore the sense amplifier circuit is made of transistor pair having an extremely balanced characteristic, cancelling the asymmetricity of current-voltage characteristic of the transistor pair to null.

We claim:  
     
       1. A sense amplifier circuit comprising first and second bit wires coupled to a memory cell, a first MOS transistor having a drain connected to said first bit wire, said second bit wire is coupled to the gate of the first MOS transistor, a second MOS transistor having a drain connected to said second bit wire, and either an N-type a P-type MOS transistor pair to compose a latch type sense amplifier circuit by coupling the gate of the second MOS transistor and the first bit wire, and coupling the sources of the first and second MOS transistors commonly to a power source wire, wherein both first and second MOS transistors are composed of a plurality of either N-type or P-type MOS transistor connected in parallel. 
     
     
       2. A sense amplifier circuit comprises forming first and second MOS transistors of a transistor pair in the same region as the first MOS transistor of the transistor pair at both sides adjacent in the column direction, and also forming the second MOS transistor in the same region as the second MOS transistor of the pair of transistors at both sides adjacent in the column direction. 
     
     
       3. A plurality of sense amplifier circuits arranged along a column direction, each of said sense amplifier circuits comprising: 
       
         at least one first MOS transistor and at least one second MOS transistor coupled to one another;  
       
       
         wherein said first MOS transistor is formed in the same continuous region as other first MOS transistors of adjacent sense amplifier circuits on both sides of said first MOS transistor in the column direction; and  
       
       
         wherein said second MOS transistor is formed in the same continuous region as other second MOS transistors of said adjacent sense amplifier circuits on both sides of said second MOS transistor in column direction.  
       
     
     
       4. The sense amplifier circuit of  claim 3 , wherein said first MOS transistor comprises a plurality of MOS transistors connected in parallel.  
     
     
       5. The sense amplifier circuit of  claim 4 , wherein said second MOS transistor comprises a plurality of MOS transistors connected in parallel.  
     
     
       6. The sense amplifier circuit of  claim 5 , wherein each of said first and second MOS transistors consists of an even number of MOS transistors.  
     
     
       7. The sense amplifier circuit of  claim 3 , wherein said first and second MOS transistors are each formed in respective first and second common areas.  
     
     
       8. The sense amplifier circuit of  claim 7 , wherein said first MOS transistors located adjacent one another in said column direction are not electrically isolated from one another. 
     
     
       9. The sense amplifier circuit of  claim 7 , wherein said second MOS transistors located adjacent one another in said column direction are not electrically isolated from one another.  
     
     
       10. The sense amplifier circuit of  claim 7 , wherein adjacent first MOS transistors have sources that are commonly connected.  
     
     
       11. The sense amplifier circuit of  claim 7 , wherein adjacent second MOS transistors have sources that are commonly connected.  
     
     
       12. The sense amplifier circuit of  claim 3 , wherein each of said sense amplifier circuits is coupled on both sides in the column direction to adjacent sense amplifier circuits by a common source.  
     
     
       13. The sense amplifier circuit of  claim 3 , wherein each of said first and second MOS transistors comprises first and second gate portions having a drain therebetween.  
     
     
       14. The sense amplifier circuit of  claim 13 , wherein the direction of current flow in said first gate portion is opposite to the direction of current flow in said second gate portion.  
     
     
       15. The sense amplifier circuit of  claim 3 , wherein a gate of said at least one first MOS transistor is coupled to a drain of said at least one second MOS transistor.  
     
     
       16. The sense amplifier circuit of  claim 3 , wherein a source of said at least one first MOS transistor is coupled to a source of said at least one second MOS transistor.  
     
     
       17. A plurality of sense amplifier circuits arranged along a column direction, each of said sense amplifier circuits comprising: 
       
         first and second MOS transistors each formed from a transistor pair having commonly connected gates, commonly connected sources, and commonly connected drains;  
       
       
         wherein said first MOS transistor is formed in the same continuous region as other first MOS transistors of adjacent sense amplifier circuits on both sides of said first MOS transistor in the column direction; and  
       
       
         wherein said second MOS transistor is formed in the same continuous region as other second MOS transistors of said adjacent sense amplifier circuits on both sides of said second MOS transistor in the column direction.  
       
     
     
       18. The sense amplifier circuit of  claim 17 , wherein the direction of current flow in one of the transistors of each transistor pair is opposite to the direction of current flow in the other transistor of said transistor pair.  
     
     
       19. The sense amplifier circuit of  claim 17 , wherein said sources of said first MOS transistor are connected to said sources of said second MOS transistor.  
     
     
       20. The sense amplifier circuit of  claim 19 , further comprising first and second bit wires coupled to said first and second MOS transistors.  
     
     
       21. The sense amplifier circuit of  claim 20 , wherein said first bit wire is connected to said drains of said first MOS transistor.  
     
     
       22. The sense amplifier circuit of  claim 21 , wherein said first bit wire is connected to said gates of said second MOS transistor.  
     
     
       23. The sense amplifier circuit of  claim 22 , wherein said second bit wire is connected to said gates of said first MOS transistor.  
     
     
       24. The sense amplifier circuit of  claim 23 , wherein said second bit wire is connected to said drains of said second MOS transistor.  
     
     
       25. A latch type sense amplifier circuit comprising: 
       
         first and second bit wires each coupled to a memory cell;  
       
         first and second MOS transistors each consisting of an even number of either N - type or P - type MOS transistors connected in parallel to each other;    
       
         said first MOS transistor having drains connected to said first bit wire and gates connected to said second bit wire;  
       
       
         said second MOS transistor having drains coupled to said second bit wire and gates connected to said first bit wire; and  
       
       
         said first and second MOS transistors having sources commonly connected to a power source wire.  
       
     
     
       26. The latch type sense amplifier circuit of  claim 25  wherein said first and second MOS transistors each consists of two N- type or P - type MOS transistors connected in parallel.    
     
     
       27. The latch type sense amplifier circuit of  claim 25  wherein said first and second MOS transistors each consist of an even number of N- type transistors and said power source wire is an earth wire.    
     
     
       28. The latch type sense amplifier circuit of  claim 25  wherein said first and second MOS transistors each consist of an even number of P- type transistors and said power source wire is a Vcc wire.