USRE38383EExpiredUtility

Method for forming a via plug in a semiconductor device

Assignee: HYUNDAI ELECTRONICS INDPriority: Sep 15, 1993Filed: Apr 16, 1999Granted: Jan 13, 2004

Est. expirySep 15, 2013(expired)· nominal 20-yr term from priority

Inventors:Kyeon K. Choi

H10W 72/944H10W 20/056H10W 20/081

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References

Claims

Abstract

A method of forming a via plug in a semiconductor device is disclosed. Metal nuclei are formed on the surface of the metal layer underlying the via hole. The metal layer, which is partially exposed between metal nuclei, is etched by means of a wet etching method, and accordingly, a plurality of etching grooves is formed on the partially exposed surface of the metal layer. As a result, the formation of such grooves has the effect of increasing the bottom surface area of the via hall, thereby increasing the adhesive strength to a contact surface of the via hall and decreasing the via resistance.

Claims

exact text as granted — not AI-modified

What is claimed is:

1. A method of forming a via plug in a semiconductor device comprises;
forming a first metal layer on a substrate and sequentially depositing a first, second and third insulating layer on the resulting substrate and then planarizing said third insulating layer;
etching a desired portion of said third, second and first insulating layer using a contact mask until said first metal layer is exposed, thereby forming a via hole;
pretreating said via hole by the dry etching method and then, forming metal nuclei on the surface of said first metal layer at the bottom of said via hole;
etching said first metal layer exposed between said metal nuclei so that a plurality of etching grooves is formed on said first metal layer; and
forming a via plug on said via hole.

2. The method of claim 1 , wherein said first metal layer exposed between said metal nuclei is etched by the wet etchant which the etching selectivity of said first metal layer is greater than said that of said metal nuclei.

3. The method of claim 1 , wherein said via plug is formed in the LPCVD reactor.

4. The method of claim 1 , wherein the magnitude of each nuclei is 500 to 1000 Å.

5. The method of claim 1 , wherein said via hole is pretreated in the RIE reactor.

6. The method of claim 1 , wherein said via hole is pretreated by a NF 3 , SF 6 or Ar sputter.

7. The method of claim 1 , wherein said etching grooves are formed using the buffered oxide etchant.

8. The method of claim 1 , wherein said metal nuclei are formed by tungsten.

9. The method of claim 1 , wherein said metal nuclei are formed by aluminum.

10. The method of claim 1 , wherein said metal nuclei are formed by copper.

11. The method of claim 1 , wherein said metal nuclei are formed by molybdenum.

12. The method of claim 1 , wherein said metal nuclei are formed by titanium.

13. The method of claim 1 , wherein said metal nuclei are formed by cobalt.

14. The method of claim 1 , wherein said metal nuclei are formed by chromium.

15. A semiconductor device comprising:

a substrate;

a conductive layer overlying the substrate;

an insulating layer overlying the conductive layer;

a via structure in the insulating layer, the via structure exposing a portion of the conductive layer;

a plurality of grooves, the plurality of grooves being on the conductive layer within the exposed portion of the conductive layer, the plurality of grooves configured to increase surface area of the conductive layer;

a plurality of conductive nuclei, the conductive nuclei being on the conductive layer and adjacent to the plurality of grooves; and

a plug layer overlying the exposed portion in the via structure.

16. The semiconductor device of claim 15 wherein the increased surface area reduces a via resistance.

17. The semiconductor device of claim 15 wherein the increased surface area increases an adhesive strength.

18. The via structure of claim 17 wherein the adhesive strength is that of the conductive layer.

19. The via structure of claim 17 wherein the adhesive strength is that of the plug layer.

20. The semiconductor device of claim 15 wherein the plurality of grooves are formed by a process including etching.

21. The semiconductor device of claim 20 wherein the etching process for forming the plurality of grooves includes a buffered oxide etching process.

22. The semiconductor device of claim 20 wherein the etching process for forming the plurality of grooves includes a wet etching process.

23. The semiconductor device of claim 15 wherein the insulating layer includes a first insulating layer overlying the conductive layer and a second insulating layer overlying the first insulating layer.

24. The semiconductor device of claim 23 wherein the insulating layer further includes a third insulating layer over the second insulating layer.

25. The semiconductor device of claim 24 wherein the third insulating layer is planarized.

26. The semiconductor device of claim 15 wherein the exposed portion of the conductive layer is pretreated by an etching method.

27. A semiconductor device comprising:

a substrate;

a conductive layer overlying the substrate;

an insulating layer overlying the conductive layer;

a via structure in the insulating layer, the via structure exposing a portion of the conductive layer;

a plurality of metal nuclei, the metal nuclei being on the conductive layer; and

a plug layer overlying the exposed portion in the via structure.

28. The semiconductor device of claim 27 wherein the plurality of metal nuclei are formed by a process including deposition.

29. The semiconductor device of claim 27 wherein each of the plurality of metal nuclei has a magnitude of 500 to 1 , 000 Å.

30. The semiconductor device of claim 27 wherein the metal nuclei comprise material selected from a group consisting of tungsten, aluminum, copper, molybdenum, titanium, cobalt, and chromium.

31. The semiconductor device of claim 15 wherein the insulating layer is planarized.

32. A via plug in a semiconductor device comprising:

a substrate;

a conductive layer overlying the substrate;

an insulating layer overlying the conductive layer, the insulating layer including a first insulating layer overlying said conductive layer and a second insulating layer overlying said first insulating layer;

a via structure in the insulating layer, the via structure exposing a portion of the conductive layer;

a plurality of grooves, the plurality of grooves being on said conductive layer and within the exposed portion of the conductive layer, the plurality of grooves configured to increase surface area of the conductive layer, the plurality of grooves being formed by a process including etching;

a plurality of conductive nuclei, the conductive nuclei being on the conductive layer and adjacent to the plurality of grooves; and

a plug layer overlying the exposed portion in the via structure.

33. A semiconductor device comprising:

a substrate;

a conductive layer overlying the substrate;

a via structure in the insulating layer, the via structure exposing a portion of the conductive layer;

a plurality of grooves, the plurality of grooves being on the conductive layer and within the exposed portion of the conductive layer, the plurality of grooves configured to increase surface area of the conductive layer;

a plurality of conductive nuclei, the conductive nuclei being on the conductive layer and adjacent to the plurality of grooves; and

a plug layer overlying the exposed portion in the via structure.

34. The semiconductor device of claim 33 wherein the plurality of grooves are formed by a process including etching.

35. The semiconductor device of claim 34 wherein the etching is wet etching.

36. The semiconductor device of claim 34 wherein the etching is an act including a buffered oxide etching process.

37. The semiconductor device of claim 33 wherein the increased surface area reduces a via resistance.

38. The semiconductor device of claim 33 wherein the increased surface area increases an adhesive strength.

39. The via structure of claim 38 wherein the adhesive strength is that of the conductive layer.

40. The via structure of claim 38 wherein the adhesive strength is that of the plug layer.

41. The semiconductor device of claim 33 wherein the exposed portion of the conductive layer is pretreated by an etching method.

42. The semiconductor device of claim 33 wherein the insulating layer further includes a third insulating layer over the second insulating layer.

43. A semiconductor device comprising:

a substrate;

a conductive layer overlying the substrate;

a via structure in the insulating layer, the via structure exposing a portion of the conductive layer;

a plurality of metal nuclei, the metal nuclei being on the conductive layer; and

a plug layer overlying the exposed portion in the via structure.

44. The semiconductor device of claim 43 wherein the metal nuclei are formed by a process including deposition.

45. The semiconductor device of claim 33 wherein the insulating layer is planarized.

46. The semiconductor device of claim 15 wherein the conductive layer comprises a metal.

47. The semiconductor device of claim 33 wherein the conductive layer comprises a metal.

48. The semiconductor device of claim 43 wherein the metal nuclei comprise material selected from the group consisting of tungsten, aluminum, copper, molybdenum, titanium, cobalt, and chromium.

49. The semiconductor device of claim 43 wherein each of the plurality of metal nuclei has a magnitude of 500 to 1 , 000 Å.

50. A via plug in a semiconductor device comprising:

a substrate;

a conductive layer overlying the substrate;

a via structure in the insulating layer, the via structure exposing a portion of the conductive layer;

a plurality of metal nuclei, the metal nuclei being on the conductive layer; and

a plug layer overlying the exposed portion in the via structure.

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