Introduction sequencer for network structure microprocessor

Abstract

The invention concerns an instructions sequencer for microprocessor wherein the sequencer presents an architecture, a circuit conception and a presents that improves the compacity and facilitates conception and adaptation operations to different instructions sets, the sequencer having a line and column architecture and very widely produced in the form of a transistor and capacitor matrix, functioning with decoding transistors, preload transistors and a matrix for defining the phases of operating cycles.

What is claimed is:  
     
       1. An instruction sequencer for a microprocessor, said sequencer having inputs for receiving binary sequencer instruction signals and outputs for supplying control signals for carrying out instructions associated with said sequencer instruction signals and controlling operation of said microprocessor, said sequencer comprising: 
       (a) sequencer inputs connected to 
       a decoding array having input column conductors which are arranged in a group of first parallel columns, each of said inputs corresponding to a respective first column of said group;  
       (b) wherein each of the first column of said group further comprises a plurality of decoding transistors, said decoding transistors of the group of the first parallel columns being furthermore aligned along rows perpendicular to the column direction with, each of the decoding transistor at the intersection of a given row and a given column having its gate connected to an input conductor corresponding to said column and having its drain connected to one row conductor of a first group of row conductors, each of which corresponds to a respective row of decoding transistors;  
       (c) wherein each of the row conductors of said first group of row conductors is connected to a respective first precharged transistors, with each of said precharged transistors having its gate controlled by a first clock signal, and further wherein each of said precharged transistors is placed along the length of a second column which is parallel to the first group of columns; and  
       (d) further wherein each row conductor is connected to a respective first capacitor, the first capacitors being placed along a third column which is parallel to said first and second columns;  
       (e) further wherein each row conductor is connected to the source of respective first sampling transistors, with each of said sampling transistors having its gate controlled by a second clock signal and having its drain connected to a row conductor of a second group of row conductors perpendicular to said columns, the first sampling transistors being furthermore placed along a fourth column which is parallel to said first, second and third columns;  
       (f) wherein each of first sampling transistor's drain is further connected to a second respective capacitor, wherein said second capacitors being placed along a fifth column which is parallel to the first, second and third columns;  
       (g) wherein each row conductor of the second group of row conductors is connected to the gate of a respective transistor taken among transistors of a sixth column parallel to said first, second, and third columns, the drain of said respective transistor being connected to an input of a respective logical controlled gate, and all the sources of said transistors of said sixth column being connected to a common point; in said decoding array and a plurality of row conductors that are arranged in said decoding array substantially perpendicular to said first parallel columns in said decoding array, each of said input column conductors connected to a defined one of said sequencer instruction signals;  
       
         a plurality of decoding elements, each associated with at least a select one of said input column conductors and at least a select one of said row conductors in a predetermined decoding pattern such that the received defined sequencer instruction signal on each of said input column conductors generates one of said decoded outputs on the one of said associated row conductors associated therewith by said decoding elements in accordance with said predetermined decoding pattern; and  
       
       (h)a gate array of logical controlled gates arranged along a seventh columnin rows and columns parallel to said first and second columns, and having an output connected first to third respective capacitors, second to a second precharged transistor, and third to a second sampling transistor, said third capacitors being placed along an eighth column, the second precharged transistors being placed along a ninth column and being controlled by a third clock signal, said second sampling transistors being placed along a tenth column and being controlled by a fourth clock signaldecoding array, each of said gates having a conductive path and a control input that renders said associated gate conductive or non- conductive, said conductive paths for said gates in each of said rows connected in series, with said rows of said gate array having inputs at one end of said rows connected to select ones of said decoded outputs of said decoding array with the rows of said decoding array substantially in line with the rows of said gate array, the columns of said gate array each having a common conductor connected to each of the control inputs for the gates in said associated column for controlling the operation thereof to be conductive or non - conductive, select ones of said gates being permanently conductive in accordance with a predetermined gate array programming scheme that defines which of said gates are permanently conductive, the common conductors in each column operable to receive clock signals that define the cyclical divisions in carrying out an instruction and each of said rows having an output at the other end thereof for outputting the input of said decoded outputs when all of said associated gates are conductive.    
     
     
       2. An instruction sequencer according to  claim 1 , wherein said controlled gates have several control inputs common to all gates and each connected to a respective conductor extending parallel to the columns of the sequencer.