Method for preventing electrostatic discharge failure in an integrated circuit package

Abstract

An integrated circuit package includes a semiconductor chip, bonding pads on the semiconductor chip, a metal lead frame containing electrically with the semiconductor chip, a plurality of wired pins wire-bonded respectively to the bonding pads, and at least one non-wired pin. The non-wired pin is wire-bonded to the metal lead frame to prevent electrostatic discharge failure of the integrated circuit package due to electrostatic discharge stressing of the non-wired pin.

I claim:  
     
       1. A method for preventing electrostatic discharge failure in an integrated circuit package which includes a semiconductor chip, bonding pads on the semiconductor chip, a metal lead frame contacting electrically with the semiconductor chip, a plurality of wired pins wire-bonded respectively to the bonding pads, and at least one non-wired pin, the electrostatic discharge failure being due to electrostatic discharge stressing of the non-wired pin, said method comprising the step of: 
       wire-bonding the non-wired pin to the metal lead frame.  
     
     
       2. A method as claimed in  claim 1 , further comprising the step of connecting electrically a power-supply electrostatic-discharge protection device to the lead frame through the semiconductor chip for discharging of current that results from electrostatic discharge stressing of the non-wired pin. 
     
     
       3. A method as claimed in  claim 1 , further comprising the step of connecting electrically a power-supply electrostatic-discharge protection device to one of the bonding pads that is for connecting electrically to a first power source, said protection device including a field effect transistor which has a drain connected electrically to said one of the bonding pads, a source for connecting electrically to a second power source and a gate connected electrically to said source thereof. 
     
     
       4. A method as claimed in  claim 3 , wherein said first power source is a positive power source, while said second power source is grounded. 
     
     
       5. A method as claimed in  claim 1 , further comprising the step of connecting electrically a power-supply electrostatic-discharge protection device to one of the bonding pads that is for connecting electrically to a first power source, said protection device including a capacitor which has a first terminal connected electrically to said one of the bonding pads, and a second terminal for connecting electrically to a second power source. 
     
     
       6. A method as claimed in  claim 5 , wherein said first power source is a positive power source, while said second power source is grounded. 
     
     
       7. A method as claimed in  claim 1 , further comprising the step of connecting electrically a power-supply electrostatic-discharge protection device to one of the bonding pads that is for connecting electrically to a first power source, said protection device including a diode which has a cathode connected electrically to said one of the bonding pads, and anode for connecting electrically to a second power source. 
     
     
       8. A method as claimed in  claim 7 , wherein said first power source is a positive power source, while said second power source is grounded. 
     
     
       9. A method as claimed in  claim 1 , further comprising the step of connecting electrically a power-supply electrostatic-discharge protection device to one of the bonding pads that is for connecting electrically to a first power source, said protection device including a first transistor having an emitter connected electrically to said one of the bonding pads via a first resistor, and a collector for connecting electrically to a second power source via a second resistor, and a second transistor having a collector connected electrically to the base of the first transistor, a base connected electrically to the collector of the first transistor, and an emitter for connecting electrically to the second power source. 
     
     
       10. A method as claimed in  claim 9 , wherein said first power source is a positive power source, while said second power source is grounded. 
     
     
       11. A method as claimed in  claim 1 , further comprising the step of connecting electrically a power-supply electrostatic-discharge protection device to one of the bonding pads that is for connecting electrically to a first power source, said protection device including a field device which has a drain connected electrically to said one of the bonding pads, a source for connecting electrically to a second power source, and a gate connected electrically to the drain thereof. 
     
     
       12. A method as claimed in  claim 11 , wherein said first power source is a positive power source, while said second power source is grounded. 
     
     
       13. A method as claimed in  claim 11 , wherein said first power source is grounded, while said second power source is a positive power source. 
     
     
       14. A method for preventing electrostatic discharge failure in an integrated circuit package which includes a semiconductor chip with a substrate, a plurality of bonding pads on the semiconductor chip, a plurality of wired pins wire- bonded to the bonding pads, and at least one non - wired pin, the electrostatic discharge failure being due to electrostatic discharge stressing of the non - wired pin, said method comprising the step of:    
         providing an electrical coupling between the non - wired pin and the substrate of the semiconductor chip.   
     
     
       15. A method as claimed in  claim 14 , further comprising the steps of: 
       
         coupling electrically a first power source node to the substrate; and  
       
         coupling electrically an electrostatic - discharge protection device between the first power source node and a second power source node.   
     
     
       16. A method as claimed in  claim 15 , wherein the protection device includes a capacitor coupled between the first and second power source nodes. 
     
     
       17. A method as claimed in  claim 16 , wherein the capacitor is a built- in capacitor.   
     
     
       18. A method as claimed in  claim 15 , wherein one of the first and second power source nodes is a positive power source node, and the other one of the first and second power source nodes is a ground node. 
     
     
       19. A method as claimed in  claim 15 , wherein the protection device includes at least an element selected from the group of a diode, a transistor, a field device and a silicon- controlled - rectifier.   
     
     
       20. A method as claimed in  claim 15 , further comprising the step of coupling electrically the protection device to one of the bonding pads. 
     
     
       21. A method as claimed in  claim 14 , wherein the substrate is either one of an N- type substrate and a P - type substrate.   
     
     
       22. A method for preventing electrostatic discharge failure in an integrated circuit package which includes a semiconductor chip, bonding pads on the semiconductor chip, a lead frame for holding the semiconductor chip, a plurality of wired pins wire- bonded to the bonding pads, and at least one non - wired pin, said method comprising the step of:    
         wire - bonding the non - wired pin into the lead frame.   
     
     
       23. An integrated circuit package protected against electrostatic discharge failure, said integrated circuit package comprising a semiconductor chip, a plurality of bonding pads on said semiconductor chip, a plurality of wired pins wire- bonded to said bonding pads, and at least one non - wired pin coupled electrically to a first power - source node.   
     
     
       24. An integrated circuit package as claimed in  claim 23 , further comprising an electrostatic- discharge protection device coupled between said first power source node and a second power source node.   
     
     
       25. An integrated circuit package as claimed in  claim 23 , wherein said semiconductor chip has a substrate, and said first power source node is coupled electrically to said substrate. 
     
     
       26. An integrated circuit package as claimed in  claim 23 , wherein said first power source node is coupled electrically to one of said bonding pads. 
     
     
       27. An integrated circuit package as claimed in  claim 24 , wherein said protection device includes a capacitor. 
     
     
       28. An integrated circuit package as claimed in  claim 27 , wherein said capacitor is a built- in capacitor.   
     
     
       29. An integrated circuit package as claimed in  claim 24 , wherein said protection device includes at least an element selected from the group of a diode, a transistor, a field device and a silicon- controlled - rectifier.   
     
     
       30. An integrated circuit package as claimed in  claim 23 , wherein said first power source node is a positive power- source node.   
     
     
       31. An integrated circuit package as claimed in  claim 23 , wherein said first power source node is a ground node.