Filter circuit for communication

Abstract

The present invention has an object to provide a filter circuit for communication generative an effective digital output as well as an analog output in a filter circuit of low electric power consumption. The function speed of an A/D converting circuit is minimized by intermittently holding an analog output signal according to an experience that peak detection can be performed by partially sampling the signal after the acquisition.

What is claimed is:  
     
       1. A filter circuit for communication comprising: 
       i) a means for addition and multiplication for  
       a) sequentially holding an analog input signal by a plurality of a  first sampling and holding circuits at a plurality of holding points,  
       b) performing a weighted addition by PN code  of said analog input signal on  at each of said holding point  points, and  
       c) outputting an addition result as an analog output signal,  
       iii) a peak detecting portion for deciding a timing to take said signal according to a peak of said analog output signal; and 
       iii) a second sampling and holding circuit for holding the analog input signal only on said timing to take said signal; and 
       iiiv) an A/D converter for converting said analog output signal into a digital signal, comprising:  
       a) a second sampling and holding circuit for holding a signal only on said timing to take said signal, and  
       b)  a quantizing portion for digitizing an output of said second sampling and holding circuit.  
     
     
       2. A filter circuit for communication as claimed in  claim 1 , wherein said second sampling and holding circuit comprises: 
       i) a plurality of third sampling and holding circuits corresponding to a plurality of peaks ;  
       ii) a plurality of switches for alternatively outputting one of outputs of said third sampling a  and holding circuits or a reference voltage; and  
       iii) a controller for controlling a holding timing of said third sampling and holding circuits and a timing of opening and closing of said switches.