System for specifying addresses by creating a multi-bit ranked ordered anchor pattern and creating next address by shifting in the direction of the superior position

Abstract

An automatic addressing technique for flexibility specifying the individual physical addresses of a plurality of devices coupled to an information bus. An anchor pattern is applied to an address bus of a plurality of address taps sufficient to uniquely specify the numbered J of devices to be attached thereto. Each device is connected to a tap on the address bus, each tap having the same number of bits. A plurality of address transform elements are serially connected to the bus, each transform element being located between adjacent tap positions. Each transform element converts the address pattern coupled to its input to another pattern capable of uniquely specifying the next address in the desired sequence. A wide variety of address sequences are available for selection, with each particular address sequence automatically determined by the related specific anchor pattern. The transform elements are passive elements, and no jumpers or settable switches are required to specify the physical addresses when configuring or reconfiguring the system.

What is claimed is:  
     
       1. A method of specifying the physical address of a plurality of devices each requiring a unique address in an array, said method comprising the steps of: 
       (a) selecting the individual  a desired address sequence;  
       (b) creating an anchor pattern representing an initial device address, said pattern having a plurality of multi-bit rank ordered fields each having a superior end position and an inferior end position;  
       (c) creating a bit pattern representing the next address in the sequence by shifting the bit pattern in each field in the direction of the superior end position of that field by an integral multiple of one rank and relocating the superior end rank position bit of the pattern to the inferior end rank position; and  
       (d) continuing step (c) until the last address in the sequence is attained  wherein each bit that is shifted beyond the superior end position is rotated back to the inferior bit position.  
     
     
       2. The method of  claim 1  wherein the integral multiple in step (c) is unity. 
     
     
       3. The method of claim  1   22 wherein said step (d)the said step of creating a bit pattern is performed a number of times equal to J−2, where J is the total number of a plurality of devices. 
     
     
       4. The method of claim  1   22 wherein said anchor pattern comprises N bits and the number of said field is i, where i is the minimum number of bits required to uniquely specify J devices. 
     
     
       5. The method of  claim 4  wherein N≧i. 
     
     
       6. The method of  claim 4  wherein N=i. 
     
     
       7. The method of  claim 4  further including the step of specifying each address with a bit of predetermined rank from each of the i fields. 
     
     
       8. A multiconductor bus device for specifying a unique physical address for each of a plurality J of devices in an array in accordance with a desired address sequence, said bus device comprising: 
       N conductors arranged in parallel and grouped into i fields, where i is the minimum number of bits required to uniquely specify J devices,  each field having a plurality of rank ordered bits with a superior end position and an inferior end position, the physical address for each device being determined by i bit values selected from one conductor of each field; and  
       a plurality of transform elements each having an input and an output coupled to said N conductors for converting a physical device address presented at the input thereto to the next physical device address in the desired address sequence at the output thereof, each transform element including means for shifting the bit pattern in each field of a physical device address presented at the input by an integral multiple of one rank and means for relocating the superior end rank position bit of the input address to the inferior rank position of the next physical device address .  
     
     
       9. The invention of  claim 8  wherein said integral multiple is unity. 
     
     
       10. The invention of  claim 8  wherein N≧i. 
     
     
       11. The invention of  claim 8  wherein N=i. 
     
     
       12. The invention of  claim 8  wherein each transform element comprises a plurality of N input terminals, a plurality of N output terminals and a plurality of N conductive paths coupled between said input terminals and said output terminals, one path coupling the input terminal corresponding to the superior end rank position of each field to the output terminal located at the inferior rank position of the corresponding field, the remaining paths effecting the bit pattern shift. 
     
     
       13. A method of producing an anchor pattern capable of being transformed into a desired sequence of physical device addresses each comprising a plurality of bits each selected from a different one of a plurality of rank ordered multi-bit fields, said method comprising the steps of: 
       (a) selecting a desired address sequence;  
       (b) converting each address of the desired sequence to a multi-field binary equivalent having a number of fields equal to the number of bits comprising each address, each field having a number of bits relatively prime to the number of bits in the preceding field; and  
       (c) arranging the bits in each binary equivalent field in a sequential order related to the manner in which the anchor pattern is transformed into the desired sequence of physical device addresses.  
     
     
       14. The method of  claim 13  wherein said anchor pattern comprises N bits and the number of said fields is i, where i is the minimum number of bits required to uniquely specify J devices. 
     
     
       15. The method of  claim 14  wherein N≧i. 
     
     
       16. The method of  claim 14  wherein N=i. 
     
     
       17. The method of  claim 14  further including the step of specifying each address with a bit of predetermined rank from each of the i fields. 
     
     
       18. A transform element comprising: 
       ( a )  a plurality of rank order inputs grouped into fields; and    
       ( b )  a plurality of rank ordered outputs grouped into the fields, each field having a superior end position and an inferior end position, wherein each rank ordered input within a field is operatively coupled to a rank ordered output shifted in that same field by an integral multiple of one rank such that each bit of the output that is shifted beyond the superior end position of each field is rotated back to the inferior bit position.   
     
     
       19. The transform element of  claim 18 , wherein an input is tapped for connecting a device. 
     
     
       20. The transform element of  claim 18 , wherein the integral multiple is unity. 
     
     
       21. The transform element of  claim 20 , wherein an input is tapped for connecting a device. 
     
     
       22. The method of  claim 2 , wherein the step of creating further includes relocating the superior end rank position bit of the pattern to the inferior end rank position. 
     
     
       23. The method of  claim 22 , wherein the step of creating is repeated to create additional addresses in the sequence. 
     
     
       24. The method of  claim 8 , wherein I is the minimum number of bits required to uniquely specify J devices.