USRE37611EExpiredUtility
Non-volatile memory system having internal data verification test mode
Est. expiryJan 22, 2016(expired)· nominal 20-yr term from priority
Inventors:Frankie F. Roohparvar
G11C 29/50004G06F 2201/81G11C 16/04G11C 29/50G11C 29/52
82
PatentIndex Score
43
Cited by
19
References
77
Claims
Abstract
A memory system including means for verifying the contents of a memory cell contained in a memory array to determine if a shift in the threshold voltage level has occurred. The memory system is placed into a test mode of operation in which an internal program or erase verify operation is executed under the control of the system's internal state machine. Once in the mode, the memory system steps through each memory cell, address by address, and reads the contents of the cell using the appropriate reference voltage for a programming or erase operation. A status register bit is set indicating successful completion of the verification operation for a block of memory cells. A register bit is also set if a cell fails the verification operation. This provides a more accurate determination of the state of a memory cell than can be achieved by performing an external read operation using read operation or data verification reference voltage levels.
Claims
exact text as granted — not AI-modifiedI claim:
1. A memory system having a standard mode of operation in which a user can program, erase, and read a memory cell, and a test mode of operation in which a non-standard mode of operation can be executed, wherein access to the test mode of operation occurs upon detection of a test mode access state different from those states which occur during the standard mode of operation, the memory system comprising:
an array of memory cells;
a test mode detector which detects the test mode access state, wherein the test mode access state is different from those states which occur during the standard mode of operation;
an internal program verify circuit which executes an internal program verify operation when the memory system is placed into an internal program verify mode of operation by the test mode detector, wherein the internal program verify circuit further comprises
a memory cell accessor which accesses a memory cell in the array;
a programmed data verification circuit which verifies data programmed into the memory cell; and
an address incrementer which increments an address of the memory cell; and
a test mode status indicator accessible to a user of the test mode which indicates success or failure of the operation executed when the memory system is placed into the internal program verify mode of operation by the test mode detector.
2. The memory system of claim 1 , wherein the programmed data verification circuit further comprises:
a threshold voltage circuit which determines a threshold voltage of the memory cell; and
a comparator which compares the threshold voltage to a program operation reference voltage.
3. The memory system of claim 1 , further comprising:
a controller for controlling execution of a memory erase operation which includes a plurality of memory erase sub-operations, the memory erase sub-operations including a regular memory pre-programming operation which accesses a memory cell in the array, programs the accessed memory cell with data indicative of a logic value of zero, verifies the programmed data, increments the address of the memory cell, and executes the regular pre-programming operation on a memory cell having an address corresponding to the incremented address, wherein the internal program verify circuit further comprises:
a flow controller for causing the controller to bypass one of the plurality of memory erase sub-operations.
4. The memory system of claim 3 , wherein the flow controller bypasses the memory erase sub-operation in response to control parameters stored in a data storage element of the memory system.
5. The memory system of claim 4 , further comprising:
a control parameter generator which generates the control parameters for bypassing the erase sub-operation in response to a control signal which initiates execution of the internal program verify operation.
6. The memory system of claim 3 , wherein the flow controller bypasses a memory erase sub-operation not involved in the internal program verify operation.
7. The memory system of claim 3 , wherein the memory system executes a high voltage stage in which a high voltage pulse is applied to a memory cell during a pre-programming operation, and wherein the test mode detector further comprises:
a high voltage control signal generator which generates a high voltage stage control signal which causes the high voltage stage to be bypassed when the memory system is placed into an internal program verify mode of operation by the test mode detector.
8. A memory system having a standard mode of operation in which a user can program, erase, and read a memory cell, and a test mode of operation in which a non-standard mode of operation can be executed, wherein access to the test mode of operation occurs upon detection of a test mode access state different from those states which occur during the standard mode of operation, the memory system comprising:
an array of memory cells;
a test mode detector which detects the test mode access state, wherein the test mode access state is different from those states which occur during the standard mode of operation;
an internal erase verify circuit which executes an internal erase verify operation when the memory system is placed into an internal erase verify mode of operation by the test mode detector, wherein the internal erase verify circuit further comprises
a memory cell accessor which accesses a memory cell in the array;
an erase verification circuit which verifies that the memory cell has been erased; and
an address incrementer which increments an address of the memory cell; and
a test mode status indicator accessible to a user of the test mode which indicates success or failure of the operation executed when the memory system is placed into the internal erase verify mode of operation by the test mode detector.
9. The memory system of claim 8 , wherein the erase verification circuit further comprises:
a threshold voltage
circuit which determines a threshold voltage of the memory cell; and
a comparator which compares the threshold voltage to an erase operation reference voltage.
10. The memory system of claim 8 , further comprising:
a controller for controlling execution of a memory erase operation which includes a plurality of memory erase sub-operations, the memory erase sub-operations including a regular memory high voltage erase operation in which a high voltage erase operation is performed on a block of memory cells, a memory cell in the block is accessed, an erased state of the accessed memory cell is verified, the address of the memory cell is incremented, and the erased state verification operation is performed on a memory cell having an address corresponding to the incremented address, wherein the internal erase verify circuit further comprises:
a flow controller for causing the controller to bypass one of the plurality of memory erase sub-operations.
11. The memory system of claim 10 , wherein the flow controller bypasses the memory erase sub-operation in response to control parameters stored in a data storage element of the memory system.
12. The memory system of claim 11 , further comprising:
a control parameter generator which generates the control parameters for bypassing the erase sub-operation in response to a control signal which initiates execution of the internal erase verify operation.
13. The memory system of claim 10 , wherein the flow controller bypasses a memory erase sub-operation not involved in the internal erase verify operation.
14. The memory system of claim 10 , wherein the memory system executes a high voltage stage in which a high voltage pulse is applied to a memory cell during an erase operation, and wherein the test mode detection means further comprises:
a high voltage control signal generator which generates a high voltage stage control signal which causes the high voltage stage to be bypassed when the memory system is placed into an internal erase verify mode of operation by the test mode detector.
15. A memory system comprising:
an array of memory cells;
a controller for controlling execution of a memory erase operation which includes a plurality of memory erase sub-operations, the memory erase sub-operations including a regular memory pre-programming operation which accesses a memory cell in the array, programs the accessed memory cell with data indicative of a logic value of zero, verifies the programmed data, increments the address of the memory cell, and executes the regular pre-programming operation on a memory cell having an address corresponding to the incremented address; and
a control modifier which modifies the operation of the controller to cause the controller to execute an internal program verify operation on the memory cells of the memory array, the internal program verify operation including accessing a memory cell in the array, verifying data programmed into the memory cell, and incrementing an address of the memory cell.
16. The memory system of claim 15 , further comprising:
an internal program verify modifier which modifies execution of the internal program verify operation so that the data programmed into the cell which is verified is data input by a user.
17. A memory system comprising:
an array of memory cells;
a controller for controlling execution of a memory erase operation which includes a plurality of memory erase sub-operations, the memory erase sub-operations including a regular memory high voltage erase operation in which a high voltage erase operation is performed on a block of memory cells, a memory cell in the block is accessed, an erased state of the accessed memory cell is verified, the address of the memory cell is incremented, and, the erased state verification operation is performed on a memory cell having an address corresponding to the incremented address; and
a control modifier which modifies the operation of the controller to cause the controller to execute an internal erase verify operation on the memory cells of the memory array, the internal erase verify operation including accessing a memory cell in the array, verifying that the memory cell has been erased, and incrementing an address of the memory cell.
18. A method of verifying a state of a memory cell contained in a memory array of a memory system, the memory system having a standard mode of operation in which a user can program, erase, and read a memory cell and a test mode of operation in which a non-standard mode of operation can be executed, wherein access to the test mode of operation occurs upon detection of a test mode access state different from those states which occur during the standard mode of operation, the method comprising:
accessing the test mode of operation;
placing the memory system into an internal program verify mode of operation;
executing an internal program verify operation when the memory system is placed into the internal program verify mode of operation, wherein the step of executing the internal program verify operation further comprises
accessing a memory cell in the array;
verifying data programmed into the memory cell; and
incrementing an address of the memory cell; and
setting a bit of a test mode status register accessible to a user of the test mode indicating success or failure of the internal program verify operation.
19. The method of claim 18 , wherein the step of verifying data programmed into the memory cell further comprises:
determining a threshold voltage of the memory cell and comparing it to a program operation reference voltage.
20. The method of claim 18 , wherein the memory system includes a controller for controlling execution of a memory erase operation which includes a plurality of memory erase sub-operations, the memory erase sub-operations including a regular memory pre-programming operation which accesses a memory cell in the array, programs the accessed memory cell with data indicative of a logic value of zero, verifies the programmed data, increments the address of the memory cell, and executes the regular pre-programming on a memory cell having an address corresponding to the incremented address, and wherein the method further comprises:
causing the controller to bypass a memory erase sub-operation not involved in the internal program verify operation.
21. The method of claim 20 , wherein the step of causing the controller to bypass a memory erase sub-operation further comprises:
generating a control signal which causes the controller to bypass the memory sub-operation in response to placing the memory system into an internal program verify mode of operation.
22. A method of verifying a state of a memory cell contained in a memory array of a memory system, the memory system having a standard mode of operation in which a user can program, erase, and read a memory cell and a test mode of operation in which a non-standard mode of operation can be executed, wherein access to the test mode of operation occurs upon detection of a test mode access state different from those states which occur during the standard mode of operation, the method comprising:
accessing the test mode of operation;
placing the memory system into an internal erase verify mode of operation;
executing an internal erase verify operation when the memory system is placed into an internal erase verify mode of operation, wherein the step of executing the internal erase verify operation further comprises
accessing a memory cell in the array;
verifying that the memory cell has been erased; and
incrementing an address of the memory cell; and
setting a bit of a test mode status register accessible to a user of the test mode indicating success or failure of the internal erase verify operation.
23. The method of claim 22 , wherein the step of verifying that the memory cell has been erased further comprises:
determining a threshold voltage of the memory cell and comparing it to an erase operation reference voltage.
24. The method of claim 22 , wherein the memory system includes a controller for controlling execution of a memory erase operation which includes a plurality of memory erase sub-operations, the memory erase sub-operations including a regular memory high voltage erase operation in which a high voltage erase operation is performed on a block of memory cells, a memory cell in the block is accessed, an erased state of the accessed memory cell is verified, the address of the memory cell is incremented, and the erased state verification operation is performed on a memory cell having an address corresponding to the incremented address, and wherein the method further comprises:
causing the controller to bypass a memory erase sub-operation not involved in the internal erase verify operation.
25. The method of claim 24 , wherein the step of causing the controller to bypass a memory erase sub-operation further comprises:
generating a control signal which causes the controller to bypass the memory sub-operation in response to placing the memory system into an internal erase verify mode of operation.
26. A method of verifying a state of a memory cell contained in a memory array of a memory system, the memory system including a controller which controls execution of a memory erase operation which includes a plurality of memory erase sub-operations, the memory erase sub-operations including a regular memory pre-programming operation which accesses a memory cell in the array, programs the accessed memory cell with data indicative of a logic value of zero, verifies the programmed data, increments the address of the memory cell, and executes the regular pre-programming on a memory cell having an address corresponding to the incremented address, the method comprising:
causing the controller to bypass the memory sub-operations not involved in an internal program verify operation; and
executing an internal program verify operation, wherein the step of executing the internal program verify operation further comprises:
accessing a memory cell in the array;
verifying data programmed into the memory cell; and
incrementing an address of the memory cell.
27. The method of claim 26 , wherein the step of verifying data programmed into the memory cell further comprises:
determining a threshold voltage of the memory cell and comparing it to a program operation reference voltage.
28. The method of claim 26 , wherein the step of executing an internal program verify operation further comprises:
setting a status register bit indicating success or failure of the internal program verify operation.
29. A method of verifying a state of a memory cell contained in a memory array of a memory system, the memory system including a controller which controls execution of a memory erase operation which includes a plurality of memory erase sub-operations, the memory erase sub-operations including a regular memory high voltage erase operation in which a high voltage erase operation is performed on a block of memory cells, a memory cell in the block is accessed, an erased state of the accessed memory cell is verified, the address of the memory cell is incremented, and the erased state verification operation is performed on a memory cell having an address corresponding to the incremented address, the method comprising:
causing the controller to bypass the memory sub-operations not involved in an internal erase verify operation; and
executing an internal erase verify operation, wherein the step of executing the internal erase verify operation further comprises:
accessing a memory cell in the array;
verifying that the memory cell has been erased; and
incrementing an address of the memory cell.
30. The method of claim 29 , wherein the step of verifying that the memory cell has been erased further comprises:
determining a threshold voltage of the memory cell and comparing it to an erase operation reference voltage.
31. The method of claim 29 , wherein the step of executing an internal erase verify operation further comprises:
setting a status register bit indicating success or failure of the internal erase verify operation.
32. A memory system comprising:
an array of memory cells;
a controller coupled to the array for performing a plurality of memory operations on the array of memory cells including an internal memory verification operation; and
an externally available status indicator coupled to the controller, wherein the controller sets the status indicator to indicate success or failure of the internal memory verification operation during a memory test operation, wherein the controller bypasses at least one memory sub - operation in order to perform the internal memory verification operation.
33. The memory system of claim 32 and further including a comparator for comparing a sensed voltage of a selected memory cell to a reference voltage, wherein the controller sets the status indicator as a function of the comparison.
34. The memory system of claim 33 , wherein the comparator compares the sensed voltage of the selected cell to a program reference voltage.
35. The memory system of claim 33 , wherein the comparator compares the sensed voltage of the selected cell to an erase reference voltage.
36. The memory system of claim 32 , wherein the controller performs each of the plurality of memory operations by executing one or more memory sub- operations according to control parameters stored in a data storage element of the memory system.
37. A memory system comprising:
an array of memory cells;
a controller coupled to the array for performing a plurality of memory operations on the array of memory cells including an internal memory verification operation; and
an externally available status indicator coupled to the controller, wherein the controller sets the status indicator to indicate success or failure of the internal memory verification operation, the controller performs each of the plurality of memory operations by executing one or more memory sub - operations according to a user - configurable flow, and
the controller bypasses at least one of the memory sub - operations in order to perform the internal memory verification operation.
38. The memory system of claim 37 , wherein the controller bypasses the memory sub- operations in response to a user configurable control parameter stored in a data storage element of the memory system.
39. The memory system of claim 37 , wherein the controller bypasses a memory erase sub- operation in order to perform a program - verify memory operation.
40. The memory system of claim 37 , wherein the controller bypasses a memory pre- programming sub - operation in order to perform an erase - verify memory operation.
41. A memory device comprising:
an array of memory cells; and
a controller coupled to the array, wherein the controller performs each of a plurality of memory operations on the array by bypassing one or more memory sub - operations according to a user - configurable flow register in order to perform an internal memory verification.
42. The memory device of claim 41 and further including an externally available status indicator coupled to the controller, wherein the controller sets the status indicator to indicate success or failure of an internal memory verification operation.
43. The memory device of claim 42 and further including a comparator for comparing a sensed voltage of a selected memory cell to a reference voltage, wherein the controller sets the status indicator according to the comparison.
44. The memory device of claim 43 , wherein the comparator compares the sensed voltage of the selected cell to a program reference voltage.
45. The memory device of claim 43 , wherein the comparator compares the sensed voltage of the selected cell to an erase reference voltage.
46. A memory device comprising:
an array of memory cells; and
a controller coupled to the array, wherein the controller performs each of a plurality of memory operations on the array by executing one or more memory sub - operations according to a user - configurable flow register, wherein the controller bypasses at least one of the memory sub - operations in order to perform an internal memory verification operation in response to a control parameter stored in a data storage element of the memory device.
47. The memory device of claim 46 , wherein the controller bypasses a memory erase sub- operation in order to perform a program - verify memory operation.
48. The memory device of claim 46 , wherein the controller bypasses a memory pre- programming sub - operation in order to perform an erase - verify memory operation.
49. A method of internally verifying a memory device comprising:
initiating an internal memory verification operation, during a test operation, based on a user - configurable control parameter;
comparing a sensed voltage of a selected cell with a reference voltage during the memory verification operation; and
setting an externally available status indicator to indicate success or failure of the comparison.
50. The method of claim 49 , wherein comparing the sensed voltage of the selected memory cell includes comparing the sensed voltage to a program reference voltage.
51. The method of claim 49 , wherein comparing the sensed voltage of the selected memory cell includes comparing the sensed voltage to an erase reference voltage.
52. The method of claim 49 , wherein initiating the internal memory verification operation includes executing one or more memory sub- operations using according to a user - configurable flow controller.
53. A method of internally verifying a memory device comprising:
initiating an internal memory verification operation based on a user - configurable control parameters stored in a data storage element of the memory device;
comparing a sensed voltage of a selected cell with a reference voltage during the memory verification operation; and
setting an externally available status indicator to indicate success or failure of the comparison, wherein initiating the internal memory verification operation includes executing one or more memory sub - operations according to a user - configurable sequence, and
wherein executing the memory sub - operations includes bypassing at least one of the memory sub - operations in response to the user configurable control parameter stored in a data storage element of the memory device.
54. The method of claim 53 , wherein bypassing at least one of the memory sub- operations includes bypassing a memory erase sub - operation in order to perform a program - verify memory operation.
55. The method of claim 53 , wherein bypassing at least one of the memory sub- operations includes bypassing a memory pre - programming sub - operation in order to perform an erase - verify memory operation.
56. A method of internally verifying a memory device comprising:
initiating an internal memory verification operation based on a user - configurable control parameter;
comparing a sensed voltage of a selected cell with a reference voltage during the memory verification operation; and
setting an externally available status indicator to indicate success or failure of the comparison, wherein comparing the sensed voltage includes setting the reference level as a function of data stored in a reference level register.
57. A method of performing an internal memory verification operation on a memory device comprising:
performing one or more memory operations during a normal mode by executing a plurality of memory sub - operations in a sequence; and
performing an internal memory verification operation during a test mode by executing a subset of the memory sub - operations, wherein performing the internal memory verification operation includes executing the subset of memory sub - operations according to a user - configurable control parameter stored in a data storage element of the memory device.
58. A method of performing an internal memory verification operation on a memory device comprising:
performing one or more memory operations during a normal mode by executing a plurality of memory sub - operations in a sequence; and
performing an internal memory verification operation during a test mode by executing a subset of the memory sub - operations, wherein performing the internal memory verification operation includes executing the subset of memory sub - operations according to a user - configurable control parameter stored in a data storage element of the memory device, wherein executing the subset of memory sub - operations includes bypassing at least one of the memory sub - operations in response to the user configurable control parameter.
59. The method of claim 58 , wherein bypassing at least one of the memory sub- operations includes bypassing a memory erase sub - operation in order to perform a program - verify memory operation.
60. The method of claim 58 , wherein bypassing at least one of the memory sub- operations includes bypassing a memory pre - programming sub - operation in order to perform an erase - verify memory operation.
61. The method of claim 58 , wherein performing the internal memory verification operation includes setting an externally available status indicator as a function of the comparison.
62. A memory system, comprising:
an internal state machine adapted to perform memory operations by sequentially executing memory sub - operations, wherein at least one memory operations involves verification of a memory cell voltage level; and
a flow register having data fixing the sequence of the memory sub - operations executed by the internal state machine, wherein the data of the flow register is a function of control parameters stored in a data storage element of the memory system.
63. The system of claim 62 and further including:
a comparator for comparing the cell voltage level with a reference voltage level; and
a user available status indicator, wherein the internal state machine sets the indicator as a function of the comparator.
64. The system of claim 63 , wherein the reference voltage level corresponds to a programmed cell voltage level.
65. The system of claim 63 , wherein the reference voltage level corresponds to an erased cell voltage level.
66. The system of claim 63 , wherein the reference voltage level is data input by a user.
67. A system, comprising:
a processor; and
a memory device connected to the processor, comprising:
an array of memory cells;
a controller coupled to the array for performing a plurality of memory operations on the array of memory cells including an internal memory verification operation; and
an externally available status indicator coupled to the controller, wherein the controller sets the status indicator to indicate success or failure of the internal memory verification operation during a memory test operation, wherein the controller bypasses at least one memory sub - operation in order to perform the internal memory verification operation.
68. The system of claim 67 , wherein the memory device further includes a comparator for comparing a sensed voltage of a selected memory cell to a reference voltage, wherein the controller sets the status indicator as a function of the comparison.
69. The system of claim 68 , wherein the comparator compares the sensed voltage of the selected cell to a program reference voltage.
70. The system of claim 68 , wherein the comparator compares the sensed voltage of the selected cell to an erase reference voltage.
71. The system of claim 67 , wherein the controller performs each of the plurality of memory operations by executing one or more memory sub- operations according to a user - configurable flow register.
72. A system, comprising:
a processor; and
a memory device connected to the processor, comprising:
an array of memory cells;
a controller coupled to the array for performing a plurality of memory operations on the array of memory cells including an internal memory verification operation; and
an externally available status indicator coupled to the controller, wherein the controller sets the status indicator to indicate success or failure of the internal memory verification operation, wherein the controller performs each of the plurality of memory operations by executing one or more memory sub - operations according to a user - configurable flow controller, and wherein the controller bypasses at least one of the memory sub - operations in order to perform the internal memory verification operation.
73. The system of claim 72 , wherein the controller bypasses the memory sub- operations in response to a user configurable control parameter stored in a data storage element of the memory system.
74. The system of claim 72 , wherein the controller bypasses a memory erase sub- operation in order to perform a program - verify memory operation.
75. The system of claim 72 , wherein the controller bypasses a memory pre- programming sub - operation in order to perform an erase - verify memory operation.
76. A flash memory device comprising:
a plurality of non - volatile memory cells;
test mode circuitry to place the flash memory device in test mode
a flow controller for causing the memory device to bypass at least one of a plurality of memory erase operations while in the test mode; and
an externally accessible status register comprising a status register bit, the status register bit is programmable to indicate success or failure of a test operation performed on the plurality of non - volatile memory cells, such that the status register bit can be read by a device external to the flash memory device.
77. A flash memory device comprising:
a plurality of non - volatile memory cells; and
a controller coupled to the array, wherein the controller performs each of a plurality of memory operations on the plurality of non - volatile memory cells by executing one or more memory sub - operations according to a programmable flow controller; and
wherein the flow controller causes the memory device to bypass at least one of the plurality of memory operations in a test mode.Join the waitlist — get patent alerts
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