Inverse Quantizer

Abstract

An inverse quantizing device includes memories which are addressed by input quantized coefficients and quantization levels and store resultant data of inverse quantization in groups such as intra DC, intra AC and non-intra. A control section discriminates the group of an input data to be inverse-quantized according to input block-type and block-strobe signals, selects one of the memories according to the discriminated result, and controls the selected memory to output the resultant data of inverse quantization stored therein. According to the device, real time processing of the input data is achieved with its simplified construction.

What is claimed is:  
     
       1. An inverse quantizing device comprising: 
       a plurality of memories for receiving input quantized coefficients and quantization levels as address data thereof and storing resultant data of inverse quantization in groups; and  
       control means for discriminating the group of an input data to be inverse-quantized in accordance with input block-type and block-strobe signals and providing a selection control signal for selecting one of said plurality of memories storing said resultant data of the discriminated group;  
       whereby said resultant data stored at the address of the selected one of said plurality of memories assigned by said quantized coefficients and said quantization levels is provided,  
       wherein said resultant data of inverse quantization are grouped into block data of intra DC, intra AC and non-intra, respectively, and said plurality of memories are an intra DC memory, an intra AC memory and a non-intra DC/AC memory.  
     
     
       2. An inverse quantizing device comprising: 
       a plurality of memories for receiving input quantized coefficients and quantization levels as address data thereof and storing resultant data of inverse quantization in groups; and  
       control means for discriminating the group of an input data to be inverse-quantized in accordance with input block-type and block-strobe signals and providing a selection control signal for selecting one of said plurality of memories storing said resultant data of the discriminated group;  
       whereby said resultant data stored at the address of the selected one of said plurality of memories assigned by said quantized coefficients and said quantization levels is provided, wherein said plurality of memories are programmable read only memories.  
     
     
       3. An inverse quantizing device comprising: 
       a plurality of memories for receiving input quantized coefficients and quantization levels as address data thereof and storing resultant data of inverse quantization in groups; and  
       control means for discriminating the group of an input data to be inverse-quantized in accordance with input block-type and block-strobe signals and providing a selection control signal for selecting one of said plurality of memories storing said resultant data of the discriminated group;  
       whereby said resultant data stored at the address of the selected one of said plurality of memories assigned by said quantized coefficients and said quantization levels is provided,  
       wherein said control means comprises:  
       a first OR gate for OR-gating said block-type and block-strobe signals and providing a first chip selection signal;  
       a first inverter for inverting said block-strobe signal;  
       a second OR gate for OR-gating the inverted block-strobe signal and said block-type signal and providing a second chip selection signal; and  
       a second inverter for inverting said block-type signal and providing a third chip selection signal.  
     
     
       4. An inverse quantization device for a decoder, comprising: 
         a storage device that stores a plurality of quantized level values, said storage device stores  (   1   )  a corresponding resultant data of the inverse quantization when an input data is a first mode type data or stores  (   2   )  a corresponding resultant data of the inverse quantization when the input data is a second mode type data; and    
         a control device discriminating the input data to be inverse - quantized according to the mode type data and controlling the storage device to determine the resultant data to be stored according to the discriminated result.   
     
     
       5. The inverse quantization device of  claim 4 , wherein the first and second mode type data comprise intra mode and non- intra mode data, respectively.   
     
     
       6. The inverse quantization device of  claim 4 , wherein said storage device stores a corresponding resultant data of the inverse quantization when the input data is a third mode type data. 
     
     
       7. The inverse quantization device of  claim 6 , wherein said input data comprises quantized coefficients and quantization levels. 
     
     
       8. The inverse quantization device of  claim 6 , wherein the first, second, and third mode type data comprise intra DC mode, non- intra mode and intra AC mode data, respectively.   
     
     
       9. The inverse quantization device of  claim 6 , wherein said storage device comprises: 
       
         a first memory storing resultant data of the inverse quantization corresponding to the first mode type data and responsive to the control device;  
       
       
         a second memory storing resultant data of the inverse quantization corresponding to the second mode type data and responsive to the control device; and  
       
       
         a third memory storing resultant data of the inverse quantization corresponding to the third mode type data and responsive to the control device. 
       
     
     
       10. The inverse quantization device of  claim 9 , wherein each of said first, second and third memories comprises a programmable read only memory. 
     
     
       11. The inverse quantization device of  claim 4 , wherein said storage device stores all resultant data of the inverse quantization. 
     
     
       12. The inverse quantization device of  claim 6 , wherein said control device comprises: 
       
         a first logic device having first and second input electrodes and performing a first logic operation;  
       
       
         a second logic device having first and second input electrodes and performing a second logic operation; and  
       
         a first inverter, wherein wherein said first logic device, said second logic device and said first inverter discriminate the input data to be inverse - quantized according to the mode type data.   
     
     
       13. The inverse quantization device of  claim 12  further comprising a second inverter coupled to the first input electrodes of said second logic device. 
     
     
       14. The inverse quantization device of  claim 13 , wherein said first and second logic devices are OR gates. 
     
     
       15. An inverse quantization device for a decoder, comprising: 
       
         a storage device that stores a plurality of quantized level values and receiving input data of at least one of quantized coefficient and quantization level as an address location for selecting a stored quantized level value; and  
       
         a control circuit, responsive to first and second control signals indicative of whether the input data is one of intra DC data, intra AC data and non - intra data, for outputting first, second and third output signals to said storage device, wherein said storage device stores one of  (   1   )  a resultant data of the inverse quantization corresponding to intra DC data in response to the first output signal,  (   2   )  a resultant data of the inverse quantization corresponding to intra AC data in response to the second output signal, and  (   3   )  a resultant data of the inverse quantization corresponding to non - intra data in response to the third output signal.   
     
     
       16. The inverse quantization device of  claim 15 , wherein said storage device is a programmable read only memory. 
     
     
       17. The inverse quantization device of  claim 15 , wherein said storage device comprises: 
       
         a first memory that stores the resultant data of the inverse quantization corresponding to intra DC data;  
       
       
         a second memory that stores the resultant data of the inverse quantization corresponding to intra AC data; and  
       
         a third memory that stores the resultant data of the inverse quantization corresponding to non - intra data.   
     
     
       18. The inverse quantization device of  claim 15 , wherein said control circuit comprises: 
       
         a first logic device having first and second input electrodes and performing a first logic operation to provide the first output signal;  
       
       
         a second logic device having first and second input electrodes and performing a second logic operation to provide the second output signal; and  
       
       
         a first inverter for providing the third output signal, wherein the first input electrodes of said first and second logic devices are coupled for receiving the second control signal, and the second input electrodes of the first and second logic devices and the first inverter are coupled for receiving the first control signal. 
       
     
     
       19. The inverse quantization device of  claim 18  further comprising a second inverter coupled to the first input electrodes of said second logic device for providing an inverted second control signal to said second logic gate. 
     
     
       20. The inverse quantization device of  claim 19 , wherein said first and second logic devices are OR gates.