Synchronous LSI memory device

Abstract

A synchronous LSI memory device, comprises memory cell array sections (BK 1, BK 2 ) each having a plurality of memory cells; a timing generating section (CLOCK MASKED SECT) for generating a first basic signal (CPOR) synchronous with a clock signal (CLK) and masked according to the status of a control signal (CKE); a signal generating section (SERIAL SYS CONTROL) for generating a second signal (CP) in synchronism with the first basic signal (CPOR) and stopping generating the second signal after a predetermined number of accesses or in response to a stop signal (MRRST, MWSTP, LADA, BSTP); and a control section (SHIFT REGISTER) for controlling the cell array sections (BK 1, BK 2 ) on the basis of outputs of the timing signal generating section and the signal generating section. In the synchronous LSI memory device, it is possible to operate the memory device whose access speed is lower than the CPU on the basis of a single high speed clock signal suitable for the CPU, so that it is possible to simplify the clock control so as to correspond to the higher speed CPU without complicating the system configuration.

What is claimed is:  
     
       1. A synchronous LSI memory device supplied with a clock signal, a stop signal and a control signal, comprising: 
       memory cell array means each having a plurality of memory cells;  
       timing generating means for generating a first basic signal synchronous with the clock signal and masked according to status of the control signal;  
       signal generating means for generating a second signal in synchronism with the first basic signal and stopping generating the second signal after a predetermined number of accesses of the memory cells or in response to the stop signal;  
       control means for controlling said memory cell array means on the basis of outputs of said timing generating means and said signal generating means;  
       mask control means for acquiring statuses of terminals in sequence into register means having a number of bits that are an even-number times larger than that obtained during a cycle interval during which a column address is inputted, outputting the acquired data in sequence, inputting the outputted data, respectively, to specific registers each having the number of bits that are an even-number times larger than that obtained during the cycle interval during which the column address is inputted, and when data inputted through the terminals are in a first status, outputting signals for setting output circuits of the register means to a high impedance status in synchronism with the second signal;  
       data holding means for, in only a write mode, acquiring the statuses of the terminals in synchronism with the second signal into registers having a plurality of bits in sequence and scrambling the acquired data on first data lines plural bits by plural bits every plural cycles; and  
       precharge means for precharging the first data lines into a write disable status every predetermined cycle interval, said data holding means and said precharge means being activated in the write mode.  
     
     
       2. The synchronous LSI memory device of claim  1 , wherein when a predetermined access length is “1”, even-number registers of said data holding means are fixed to a status that is the same as when masked data are acquired. 
     
     
       3. A synchronous LSI memory device supplied with a clock signal, a stop signal and a control signal, comprising: 
       memory cell array means each having a plurality of memory cells;  
       timing generating means for generating a first basic signal synchronous with the clock signal and masked according to status of the control signal;  
       signal generating means for generating a second signal in synchronism with the first basic signal and stopping generating the second signal after a predetermined number of accesses of the memory cells or in response to the stop signal;  
       control means for controlling said memory cell array means on the basis of outputs of said timing generating means and said signal generating means;  
       mask control means for acquiring statuses of terminals in sequence into register means having a number of bits that are an even-number times larger than that obtained during a cycle interval during which a column address is inputted, outputting the acquired data in sequence, inputting the outputted data, respectively, to specific registers each having the number of bits that are an even-number times larger than that obtained during the cycle interval during which the column address is inputted, and when data inputted through the terminals are in a first status, outputting signals for setting output circuits of the register means to a high impedance status in synchronism with the second signal;  
       read mask registers for acquiring, in a read mode, the statuses of the second terminals into a plurality of registers in sequence in synchronism with the second signal, and outputting the acquired data to data lines in sequence; and  
       potential fixing means for fixing, in a write mode, potentials of the data lines to set output circuits connected to the data lines to a high impedance status.  
     
     
       4. The synchronous LSI memory device of claim  3 , wherein when a predetermined access length is “1”, even-number registers of said read mask registers having a bit number length half of a word length are fixed to a mask data output status. 
     
     
       5. A synchronous LSI memory device supplied with a clock signal, a stop signal, and a control signal, comprising: 
       memory cell array means each having a plurality of memory cells;  
       timing generating means for generating a first basic signal synchronous with the clock signal and masked according to status of the control signal;  
       signal generating means for generating a second signal in synchronism with the first basic signal and stopping generating the second signal after a predetermined number of accesses of the memory cells or in response to the stop signal; and  
       control means for controlling said memory cell array means on the basis of outputs of said timing generating means and said signal generating means,  
       wherein the stop signal is outputted subsequent to a predetermined number of accesses of the memory cells after the memory cells have been precharged by a precharge means.  
     
     
       6. The synchronous LSI memory device of claim  5 , wherein when a write latency is “1”, the stop signal is outputted in a first clock cycle immediately after a write disable mode has been changed to a write enable mode. 
     
     
       7. A synchronous LSI memory device supplied with a clock signal, a stop signal, and a control signal, comprising: 
       memory cell array means each having a plurality of memory cells;  
       timing generating means for generating a first basic signal synchronous with the clock signal and masked according to status of the control signal;  
       signal generating means for generating a second signal in synchronism with the first basic signal and stopping generating the second signal after a predetermined number of accesses of the memory cells or in response to the stop signal; and  
       control means for controlling said memory cell array means on the basis of outputs of said timing generating means and said signal generating means, wherein the number of predetermined accesses is counted on the basis of a signal for selecting bits n-bits by n-bits by interleaving an m(=n+n)-bit register having two sets of n-bit registers.  
     
     
       8. A synchronous LSI memory device supplied with a clock signal, a stop signal, and a control signal, comprising: 
       memory cell array means each having a plurality of memory cells;  
       timing generating means for generating a first basic signal synchronous with the clock signal and masked according to status of the control signal;  
       signal generating means for generating a second signal in synchronism with the first basic signal and stopping generating the second signal after a predetermined number of accesses of the memory cells or in response to the stop signal; and  
       control means for controlling said memory cell array means on the basis of outputs of said timing generating means and said signal generating means,  
       wherein when a plurality of said memory cells are accessed in series, a plurality of serially accessed memory cells can be accessed simultaneously.  
     
     
       9. The synchronous LSI memory device of claim  8 , wherein when a plurality of said cell array means are accessed simultaneously, a plurality of data buffers whose number is a half of that required when a single cell array is accessed are activated in the respective cell arrays means. 
     
     
       10. A synchronous LSI memory device supplied with a clock signal, a stop signal, and a control signal, comprising: 
       memory cell array means each having a plurality of memory cells;  
       timing generating means for generating a first basic signal synchronous with the clock signal and masked according to status of the control signal;  
       signal generating means for generating a second signal in synchronism with the first basic signal and stopping generating the second signal after a predetermined number of accesses of the memory cells or in response to the stop signal; and  
       control means for controlling said memory cell array means on the basis of outputs of said timing generating means and said signal generating means,  
       wherein the second signal is divided into a plurality of signals according to use so as to be controlled individually.  
     
     
       11. A synchronous memory device operable in response to a clock signal, bank select address signals, address signals, /CS ( inverted Chip Select Signal ),  /RAS  ( inverted Row Address Strobe signal ),  /CAS  ( inverted Column Address Strobe signal )  and /WE  ( inverted Write Enable signal ),  and outputting data to DQ  ( Data Input/Output )  terminal, comprising:    
       
         a memory cell array divided into a plurality of banks, each of the banks being precharged and being activated in response to the bank select address signals, each of the banks having a plurality of memory cells arranged in a matrix form, and each of the memory cells being selected in response to address signals;  
       
       
         a mode register configured to store an operand code; and  
       
       
         a control circuit operable in response to the clock signal, the bank select address signals, the address signals, the inverted Chip Select signal, the inverted Row Address Strobe signal, the inverted Column Address Strobe signal, and the inverted Write Enable signal, the control circuit configured to render the bank select address signals and the address signals to be valid and to set the operand code to the mode register when the inverted Chip Select signal is in a low level, the inverted Row Address Strobe signal is in the low level, the inverted Column Address Strobe signal is in the low level, and the inverted Write Enable signal is in the low level and when the clock signal changes,  
       
       
         wherein the operand code is issued when all of the banks of the memory cell array are precharged. 
       
     
     
       12. The synchronous memory device of claim  11 , wherein all of the banks of the memory cell array are precharged when the inverted Chip Select signal is in the low level, the inverted Row Address Strobe signal is in the low level, the inverted Column Address Strobe signal is in a high level, the inverted Write Enable signal is in the low level, and at least one of the address signals is in the high level and when the clock signal changes, and wherein the control circuit renders the bank select address signal to the don't care. 
     
     
       13. The synchronous memory device of claim  12 , wherein the banks of the memory cell array are deactivated to be precharged in response to the bank select address signal when the inverted Chip Select signal is in the low level, the inverted Row Address Strobe signal is in the low level, the inverted Column Address Strobe signal is in the high level, the inverted Write Enable signal is in the low level, and at least one of the address signals is in the low level and when the clock signal changes, and wherein the control circuit renders the bank select address to be valid. 
     
     
       14. The synchronous memory device of claim  11 , wherein a row of the memory cell array within the banks is selectively activated in response to the bank select address signal and the row address signal when the inverted Chip Select signal is in the low level, the inverted Row Address Strobe signal is in the low level, the inverted Column Address Strobe signal is in a high level, the inverted Write Enable signal is in the high level and when the clock signal changes, and wherein the control circuit renders the bank select address to be valid and renders the address signal to be a row address signal. 
     
     
       15. The synchronous memory device of claim  12 , wherein a row of the memory cell array within the banks is selectively activated in response to the bank select address signal and a row address signal when the inverted Chip Select signal is in the low level, the inverted Row Address Strobe signal is in the low level, the inverted Column Address Strobe signal is in the high level, the inverted Write Enable signal is in the high level, and when the clock signal changes, and wherein the control circuit renders the bank select address signal to be valid and renders the address signal to be a row address signal. 
     
     
       16. The synchronous memory device of claim  13 , wherein a row of the memory cell array within the banks is selectively activated in response to the bank select address signal and a row address signal when the inverted Chip Select signal is in the low level, the inverted Row Address Strobe signal is in the low level, the inverted Row Address Strobe signal is in the low level, the inverted Column Address Strobe signal is in the high level, the inverted Write Enable signal is in the high level, and when the clock signal changes, and wherein the control circuit renders the bank select address signal to be valid and renders the address signal to be a row address signal. 
     
     
       17. The synchronous memory device of claim  11 , wherein: 
         the synchronous memory is operable further in response to /DOM  ( Data Input/Output Mask signal );  
       
         the data is output in synchronization with the clock signal and an output of the data is enabled when the Data Input/Output Mask signal is in a high level and the clock signal changes, and the output of the data is disabled when the Data Input/Output Mask signal is in the low level and the clock signal changes; and  
       
       
         the control circuit renders the bank select address signals, the address signals, the inverted chip Select signal, the inverted Row Address Strobe signal, the inverted Column Address Strobe signal, and the inverted Write Enable signal to be don't care when the Data Input/Output Mask is asserted. 
       
     
     
       18. The synchronous memory device of claim  11 , wherein: 
         the synchronous memory is operable further in response to CKE  ( Clock Enable signal );  
       
         the data is output in synchronization with the clock signal; and  
       
       
         the control circuit suspends input of the clock signal when the Clock Enable is in the low level. 
       
     
     
       19. The synchronous memory device of claim  18 , wherein during a time when the control circuit suspends the input of the clock signal, an inputting of any command is suspended. 
     
     
       20. The synchronous memory device of claim  19 , wherein a series of data is outputted beginning after a designated latency and ending after a module length of data are output, and wherein the module length is selected from a set of predetermined module length groups. 
     
     
       21. The synchronous memory device of claim  18 , further comprising a refresh control circuit for controlling a refresh operation of the memory cell array, wherein the control circuit interprets the status of control signals as SELF- REFRESH when the inverted Chip Select signal is in the low level, the inverted Row Address Strobe signal is in the low level, the inverted Column Address Strobe signal is in the low level, the inverted Write Enable signal is in a high level, and the Clock Enable signal is in the low level and when the clock signal changes, and activates the refresh control circuit.   
     
     
       22. The synchronous memory device of claim  19 , further comprising a refresh control circuit for controlling a refresh operation of the memory cell array, wherein the control circuit interprets the status of control signals as SELF- REFRESH when the inverted Chip Select signal is in the low level, the inverted Row Address Strobe signal is in the low level, the inverted Column Address Strobe signal is in the low level, the inverted Write Enable signal is in a high level, and the Clock Enable signal is in the low level and when the clock signal changes, and activates the refresh control circuit.   
     
     
       23. The synchronous memory device of claim  20 , further comprising a refresh control circuit for controlling a refresh operation of the memory cell array, wherein the control circuit interprets the status of control signals as SELF- REFRESH when the inverted Chip Select signal is in the low level, the inverted Row Address Strobe signal is in the low level, the inverted Column Address Strobe signal is in the low level, the inverted Write Enable signal is in a high level, and the Clock Enable signal is in the low level and when the clock signal changes, and activates the refresh control circuit.   
     
     
       24. The synchronous memory device of claim  11 , wherein the control circuit renders the address signals to be valid and renders the data in the memory cell array to be read when the inverted Chip Select signal is in the low level, the inverted Row Address Strobe signal is in a high level, the inverted Column Address Strobe signal is in the low level, and the inverted Write Enable signal is in the high level and when the clock signal changes. 
     
     
       25. The synchronous memory device of claim  24 , further comprising an output buffer for outputting the data to Data Input/Output terminal, wherein a series of data is outputted beginning after a designated latency and ending after a module length of data is output and wherein the module length is selected from a set of predetermined module length groups. 
     
     
       26. The synchronous memory device of claim  25 , wherein the module length is variable. 
     
     
       27. The synchronous memory device of claim  25 , wherein the latency is variable.