Delay circuit device

Abstract

A delay circuit device is described which includes a first delay circuit series that can extract output from any position on a transmission path of a signal, a second delay circuit series that can enter input from any position on a transmission path of a signal, and a control circuit having an input terminal, an output terminal, and an input/output control terminal for signals. The first delay circuit series and the second delay circuit series are arranged such that their signal transmission paths are aligned in opposite directions; the output of the first delay circuit series and the input of the second delay circuit series passing by way of the control circuit and being sequentially connected to each other from the side close to the input of the first delay circuit series and from the side close to the output of the second delay circuit series. A first signal is inputted to the first delay circuit series, a second signal is inputted to the control circuit at an arbitrary subsequent time, and the first signal in the first delay circuit series is transferred to the second delay circuit series.

What is claimed is:  
     
       1. A delay circuit device comprising: 
       a first delay circuit series that can extract output from any position on a transmission path of a signal, a second delay circuit series that can enter input from any position on a transmission path of a signal, and a control circuit means having an input terminal, an output terminal, and an input/output control terminal for signals;  
       wherein said first delay circuit series and said second delay circuit series are arranged such that their signal transmission paths are aligned in opposite directions; output of said first delay circuit series and input of said second delay circuit series being passed through the control circuit means and sequentially connected to each other from the side close to the input of said first delay circuit series and from the side close to the output of said second delay circuit series; and  
       wherein a first signal is inputted to said first delay circuit series, a second signal is inputted to said control circuit at any time thereafter, and said first signal in said first delay circuit series is transferred to said second delay circuit series.  
     
     
       2. A delay circuit device according to claim  1  wherein a second signal is inputted to said control circuit means, said first signal on said first delay circuit series is transferred to said second delay circuit series, and said first signal on said first delay circuit series is removed from said first delay circuit series. 
     
     
       3. A delay circuit device according to claim  1  wherein said first delay circuit series and said second delay circuit series are constructed such that delay times of both series are equal. 
     
     
       4. A delay circuit device according to claim  1  wherein voltage impressed to said first delay circuit series and said second delay circuit series is supplied from a constant-voltage power source. 
     
     
       5. A delay circuit device according to claim  1  wherein, in a circuit having a plurality of voltage sources, voltage impressed to said first delay circuit series and said second delay circuit series is supplies from a relatively high voltage source. 
     
     
       6. A delay circuit device according to claim  1  further comprising a reception circuit means for external signals, an amplification circuit means, a first delay circuit means having a delay time equal to said reception circuit means, and a second delay circuit means having a delay time equal to said amplification circuit means; and where a first signal is inputted to said first delay circuit series after sequentially progressing through said reception circuit means, said first delay circuit means, and said second delay circuit means; a first signal is inputted to said control circuit means after passing through said reception circuit means; and output of said second delay circuit series is inputted to said amplification circuit means. 
     
     
       7. A delay circuit device according to claim  1  wherein said first signal and said second signal are composed of synchronous signal pulses having a fixed cycle within a prescribed permissible range of error; said second signal being a pulse later than said first pulse by a prescribed number of pulses. 
     
     
       8. A delay circuit device according to claim  1  further comprising a third delay circuit means capable of selecting from a plurality of delay times according to a plurality of control signals and a fourth delay circuit means having a configuration equivalent to said third delay circuit means; said third delay circuit means being arranged serially in the input path of said first delay circuit series; said fourth delay circuit means being arranged serially in the output path of said second delay circuit series; and input times of said third delay circuit means and said fourth delay circuit means being controlled so as to be equal. 
     
     
       9. A delay circuit device according to claim  1  wherein said first delay circuit series and said second delay circuit series are principally composed of inverters and NANDs. 
     
     
       10. A delay circuit device according to claim  1  wherein internal circuits of said first delay circuit series and internal circuits of said second delay circuit series are composed of circuit layouts having a mirror-image relation to each other. 
     
     
       11. A delay circuit device according to claim  1  wherein said first signal and said second signal are synchronous signals or pulse signals of continuous clock pulses. 
     
     
       12. A delay circuit device according to claim  6  wherein the sum of delay times of said first delay and said second delay circuit means is set to a time equal to the signal width of external signals subtracted from the sum of the delay time of said reception circuit means and the delay time of said amplification circuit means; a first signal is inputted to said first delay circuit series after having sequentially passed through said reception circuit means, said first delay circuit means, and said second delay circuit means; said first signal is inputted to said control circuit means after passing through said reception circuit means; and the output of said second delay circuit series is inputted to said amplification circuit means after having been inverted. 
     
     
       13. A delay circuit device according to claim  6  configured to allow regulation of a delay time of said first delay circuit means by an electrical signal, and comprising a fuse circuit means for generating said electrical signal. 
     
     
       14. A delay circuit device according to claim  1  further comprising a switching circuit means for switching the path of a signal to a route that passes directly from said reception circuit means to said amplification circuit means without passing through said first delay circuit series, said second delay circuit series, said first delay circuit means, and said second delay circuit means when the interval between said first signal and said second signal is longer than the sum of the maximum delay time of said first delay circuit series, the delay time of said first delay circuit, and the delay time of said second delay circuit means; and for switching the path of a signal from a route that passes directly from said reception circuit means to said amplification path to a route that passes through said first delay circuit series, said second delay circuit series, said first delay circuit means, and said second delay circuit means when the interval between said first signal and said second signal is shorter than the sum of the maximum delay time of said first delay circuit series, the delay time of said first delay circuit means, and the delay time of said second delay circuit means. 
     
     
       15. A delay circuit device according to claim  14  wherein said switching circuit means includes a hysteresis. 
     
     
       16. A delay circuit device according to claim  6  further comprising an activation circuit means that generates a first activation signal and a second activation signal; and wherein said first activation signal activates said reception circuit means; said second activation signal activates input to said first delay circuit series, said second delay circuit series, said first delay circuit means, and said second delay circuit means; and when either said first or said second activation signal is in an inactive state, all signals within said first delay circuit series are removed. 
     
     
       17. A delay circuit device according to claim  16  wherein said activation circuit means is controlled by either an active signal or a power-down signal of a synchronous memory circuit device. 
     
     
       18. A delay circuit device according to claim  6  further comprising a clock output control circuit means that generates an output control signal; and wherein said output control signal controls the output of said first signal or said second signal from said amplification circuit means; and said output control signal is controlled by a read mode signal, a burst mode signal, and a CAS latency signal of said synchronous memory circuit device. 
     
     
       19. A delay circuit device according to claim  1  further comprising a clock pulse mode signal generation circuit means that generates a clock pulse mode signal; and wherein said clock pulse mode signal switches the path of a signal from a route that passes directly from said reception circuit means to said amplification circuit means or to a route that passes through said first delay circuit series, said second delay circuit series, said first delay circuit means, and said second delay circuit means. 
     
     
       20. A delay circuit device according to claim  1  configured to allow regulation of the delay time of said first delay circuit means by an electrical signal; said electrical signal being a signal that eliminates phase difference between an external signal and the output of said amplification circuit means; and further comprising a phase comparison circuit means for generating said electrical signal. 
     
     
       21. A delay circuit device according to claim  1  wherein the delay time of said second delay circuit series is set by a load regulation circuit means connected to said second delay circuit series. 
     
     
       22. A delay circuit device according to claim  21  wherein load of said load regulation circuit means is controlled by a signal for controlling load. 
     
     
       23. A delay circuit device according to claim  1  wherein said second delay circuit series is made up of a plurality of delay circuit series, this plurality of delay circuit series making up said second delay circuit series each having a prescribed delay time ratio with respect to said first delay circuit series; and said first signal and said second signal having various ratios with respect to the cycle of a synchronous signal. 
     
     
       24. A delay circuit device according to claim  6  wherein a fifth delay circuit means is arranged in the next section following said second delay circuit series; the delay time of said first delay circuit series and the delay time of said second delay circuit series are set at a prescribed ratio; the ratio between the sum of the delay time of said first delay circuit means and the delay time of said second delay circuit means and the delay time of said fifth delay circuit means is set to equal the ratio between the delay time of said first delay circuit series and the delay time of said second delay circuit series; and the output of said fifth delay circuit means, the OR output of the output of said fifth delay circuit means and the output of said reception circuit means, the output of an RS flip-flop that takes as reset, inputs the output of said fifth delay circuit means and the output of said reception circuit means, or frequency-divided output of said OR output is inputted to said amplification circuit means. 
     
     
       25. A delay circuit device according to claim  6  wherein a fifth delay circuit means is arranged in the next section following said second delay circuit series; said second delay circuit series is made up of a plurality of delay circuit series; the delay time of said first delay circuit series and the delay time of said second delay circuit series are set at a prescribed ratio; the ratio between the sum of the delay time of said first delay circuit means and the delay time of said second delay circuit means and the delay time of said fifth delay circuit means is set to equal the ratio between the delay time of said first delay circuit series and the delay time of said second delay circuit series; and the output of said fifth delay circuit means, OR output of the output of said fifth delay circuit means and the output of said reception circuit means, the output of an RS flip-flop that takes as reset and set inputs the output of said fifth delay circuit means and the output of said reception circuit means, or frequency-divided output of said OR output is inputted to said amplification circuit means. 
     
     
       26. A delay circuit device according to claim  25  wherein said second delay circuit series is made up of two delay circuit series; the delay time of said first delay circuit series and the delay time each of said two delay circuit series of said second delay circuit series are set at a 2-to-1 ratio; the ratio between the sum of the delay time of said first delay circuit means and the delay time of said second delay circuit means and the delay time of said fifth delay circuit means is set to equal the ratio between the delay time of said first delay circuit series and the delay time of said second delay circuit series; the output of said first delay circuit series is inputted by way of said control circuit means; OR output of the output of said first delay circuit series and the output of said second delay circuit series is inputted to said fifth delay circuit means; and OR output of the output of said fifth delay circuit means and the output of said reception circuit means, the output of an RS flip-flop that takes as reset and set inputs the output of said fifth delay circuit means and the output of said reception circuit means, or the frequency-divided output of said OR output is inputted to said amplification circuit means. 
     
     
       27. A delay circuit device according to claim  24  wherein said second delay circuit series is made up of two delay circuit series; the delay time of said first delay circuit series and the delay time each of said two delay circuit series of said second delay circuit series are set at a 2-to-1 ratio; the ratio between the sum of the delay time of said first delay circuit means and the delay time of said second delay circuit means and the delay time of said fifth delay circuit means is set to equal the ratio between the delay time of said first delay circuit series and the delay time of said second delay circuit series; the output of said first delay circuit series is inputted by way of said control circuit means; OR output of the output of said first delay circuit series and the output of said second delay circuit series is inputted to said fifth delay circuit means; and OR output of the output of said fifth delay circuit means and the output of said reception circuit means, the output of an RS flip-flop that takes as reset and set inputs the output of said fifth delay circuit means and the output of said reception circuit means, or the frequency-divided output of said OR output is inputted to said implication circuit means. 
     
     
       28. A delay circuit device according to claim  1  wherein the ratio between the delay times of said first delay circuit series and said second delay circuit series is set at the ratio between the number of circuits making up said first delay circuit series and the number of circuits making up said second delay circuit series. 
     
     
       29. A delay circuit device according to claim  6  wherein said first delay circuit series and said second delay circuit series are in a loop formation; and which further comprises a counter means which, from an arbitrary time after said first delay circuit series inputs said first signal and until said control circuit means inputs said second signal, counts the number of times said first signal completes laps around said first delay circuit series formed as a loop; and when said control circuit means inputs said second signal, causes said first signal on said first delay circuit series to be transferred to said second delay circuit series, and at the same time, subtracts from the counted number of laps each time said first signal completes a lap around said second delay circuit series, and when said first signal has completed the same number of laps around said second delay circuit series as completed around said first delay circuit series, causes said first signal to be outputted from said second delay circuit series. 
     
     
       30. A delay circuit device according to claim  29  wherein said counter means comprises an adder that counts the number of laps completed by said first signal around said first delay circuit series formed as a loop until said control circuit means inputs said second signal; a transmitter that transfers said first signal on said first delay circuit series to said second delay circuit series when said control circuit means inputs said second signal, and at the same time, outputs the number of laps counted by said adder; and a subtracter that subtracts from said outputted number of laps each time said first signal completes a lap around said second delay circuit series, and when said first signal has completed the same number of laps around said second delay circuit series as completed around said first delay circuit series, outputs said first signals from said second delay circuit series. 
     
     
       31. A delay circuit device according to claim  22  further comprising a switching circuit means that, when said counter indicates a maximum value, switches the path of a signal to a route that passes directly from said reception circuit means to said amplification circuit means without passing through said first delay circuit series, said second delay circuit series, said first delay circuit means and said second delay circuit means; and when a second signal is inputted when said counter means indicates a value less than a maximum value, switches the path of a signal from a route that directly passes from said reception circuit means to said amplification circuit means to a route that passes through said first delay circuit series, said second delay circuit series, said first delay circuit means, and said second delay circuit means. 
     
     
       32. A delay circuit device according to claim  31  wherein said switching circuit means includes a hysteresis. 
     
     
       33. A delay circuit device comprising: 
       
         a first delay circuit series including a plurality of first unit delay circuits coupled in series such that an output of a preceding one of said first unit delay circuits is electrically connected to an input of a succeeding one of said first unit delay circuits, an initial one of said first unit delay circuits being provided to receive a clock to be transmitted; and  
       
       
         a second delay circuit series including a plurality of second unit delay circuits coupled in series such that an output of a preceding one of said second unit delay circuits is electrically connected to an input of a succeeding one of said second unit delay circuits;  
       
       
         wherein said first and second delay circuit series are arranged such that an initial one to a last one of said first unit delay circuits are associated respectively with a last one to an initial one of said second unit delay circuits; and  
       
       
         wherein a first clock that is transmitted through said first delay circuit series is, in response to an appearance of a second clock that is to be next transmitted through said first delay circuit series, passed from a first unit delay circuit that is outputting said first clock to an associated one of said second unit delay circuits and then transmitted through remaining ones of said second unit delay circuits and outputted from the last one of said second unit delay circuits. 
       
     
     
       34. The device as claimed in claim  33 , wherein said first and second delay circuit series are arranged such that clock transmission paths of said first and second delay circuit series are aligned in an opposite direction to each other. 
     
     
       35. The device as claimed in claim  34 , wherein a delay time of each of said first unit delay circuits is substantially equal to that of each of said second unit delay circuits. 
     
     
       36. The device as claimed in claim  34 , wherein a delay time of each of said first unit delay circuits is larger than that of each of said second unit delay circuits. 
     
     
       37. The device as claimed in claim  34 , further comprising a first circuit supplying the clock to be transmitted to said first delay circuit series, and a second circuit receiving the clock outputted from said second delay circuit series. 
     
     
       38. The device as claimed in claim  34 , wherein said first clock is no longer transmitted through said first delay circuit series when said first clock is passed to said second delay circuit series. 
     
     
       39. A delay circuit device comprising: 
       
         a first delay circuit series including a plurality of first unit delay circuits coupled in series such that an output of a preceding one of said first unit delay circuits is electrically connected to an input of a succeeding one of said first unit delay circuits, an initial one of said first unit delay circuits being provided to receive a clock to be transmitted; and  
       
       
         a second delay circuit series including first and second circuit parts, said first circuit part including a plurality of second unit delay circuits coupled in series such that an output of a preceding one of said second unit delay circuits is electrically connected to an input of a succeeding one of said second unit delay circuits, and said second circuit part including a plurality of third unit delay circuits coupled in series such that an output of a preceding one of said third unit delay circuits is electrically connected to an input of a succeeding one of said third unit delay circuits;  
       
         wherein said first and second unit delay circuit series are arranged such that odd - numbered ones of said first unit delay circuits are associated respectively with said second unit delay circuits and even - numbered ones of said first unit delay circuits are associated respectively with said third unit delay circuits; and    
       
         wherein a first clock that is transmitted through said first delay circuit series is, in response to an appearance of a second clock that is to be next transmitted through said first delay circuit series, passed from a first unit delay circuit that is outputting said first clock to an associated one of said second or third unit delay circuits and then transferred through remaining ones of said second or third unit delay circuits and outputted from the last one of one of said second or third unit delay circuits. 
       
     
     
       40. The device as claimed in claim  39 , further comprising a gate circuit coupled to said first and second circuit parts to perform a logical sum on outputs of said first and second circuit paths. 
     
     
       41. The device as claimed in claim  39 , wherein said first clock is no longer transmitted through said first delay circuit series when said first clock is passed to one of said first and second circuit parts of said second delay circuit series. 
     
     
       42. A delay circuit device comprising: 
       
         a first delay circuit series including a plurality of first unit delay circuits coupled in series such that an output of a preceding one of said first unit delay circuits is electrically connected to an input of a succeeding one of said first unit delay circuits, an initial one of said first unit delay circuits being provided to receive a clock to be transmitted; and  
       
       
         a second delay circuit series including a plurality of second unit delay circuits coupled in series such that an output of a preceding one of said second unit delay circuits is electrically connected to an input of a succeeding one of said second unit delay circuits;  
       
       
         wherein said first and second delay circuit series are arranged such that an initial one to a last one of said first unit delay circuits are associated respectively with a last one to an initial one of said second unit delay circuits; and  
       
       
         wherein a first clock that is fed to said initial one of the first unit delay circuits and then transmitted through said first delay circuit series is passed from a first unit delay circuit that is outputting said first clock to an associated one of said second unit delay circuits in response to a second clock signal, said second clock signal being fed to said initial one of the first unit delay circuits and transmitted through said first delay circuit series one clock cycle after said first clock signal, said first clock signal then transmitted through remaining ones of said second unit delay circuits and outputted from the last one of said second unit delay circuits. 
       
     
     
       43. The device as claimed in claim  42 , wherein said first and second delay circuit series are arranged such that clock transmission paths of said first and second delay circuit series are aligned in an opposite direction to each other. 
     
     
       44. The device as claimed in claim  43 , wherein a delay time of each of said first unit delay circuits is substantially equal to that of each of said second unit delay circuits. 
     
     
       45. The device as claimed in claim  43 , wherein a delay time of each of said first unit delay circuits is larger than that of each of said second unit delay circuits. 
     
     
       46. The device as claimed in claim  43 , further comprising a first circuit supplying the clock to be transmitted to said first delay circuit series, and a second circuit receiving the clock outputted from said second delay circuit series. 
     
     
       47. The device as claimed in claim  43 , wherein said first clock is no longer transmitted through said first delay circuit series when said first clock is passed to said second delay circuit series. 
     
     
       48. A method of generating an internal signal having no phase difference with an external signal, said method comprising the steps of: 
       
         delaying the external signal to produce a first delayed signal;  
       
       
         delaying the first delayed signal to produce a second delayed signal;  
       
       
         transmitting the second delayed signal through a first delay circuit series including a plurality of first unit delay circuits coupled in series such that an output of a preceding one of said first unit delay circuits is electrically connected to an input of a succeeding one of said first unit delay circuits, an initial one of said first unit delay circuits receiving the second delayed signal;  
       
       
         comparing the second delayed signal transmitted through the first delay circuit series with the first delayed signal at an output of the first unit delay circuits;  
       
       
         supplying the second delayed signal appearing at an output of one of the first unit delay circuits to a second delay circuit series as a third delayed signal based on the step of comparing, wherein the second delay circuit series includes a plurality of second unit delay circuits coupled in series such that an output of a preceding one of said second unit delay circuits is electrically connected to an input of a succeeding one of said second unit delay circuits, and said second delay circuit series is arranged such that an initial one to a last one of said second unit delay circuits are associated respectively with a last one to an initial one of said first unit delay circuits, and wherein the third delayed signal is supplied to one of the second unit delay circuits associated with the first unit delay circuit from which the third delayed signal was output;  
       
       
         transmitting the third delayed signal through remaining ones of said second unit delay circuits to generate a fourth delayed signal; and  
       
       
         delaying the fourth delayed signal to produce the internal signal having no phase difference with the external signal. 
       
     
     
       49. A method according to claim  48 , wherein the amount of delay added to the second delayed signal from the first delayed signal is equal to the sum of the amount of delay added to the first delayed signal from the external signal and the amount of delay added to the fourth delayed signal to produce the internal signal. 
     
     
       50. A method according to claim  48 , wherein the third delayed signal is supplied to the second delay circuit series when the first delayed signal goes to a high level.