Planarization of a gate electrode for improved gate patterning over non-planar active area isolation

Abstract

The present invention is a process for providing a planarized transistor gate on a non-planar starting substrate, by depositing a layer of planarized conductive polysilicon material overlying neighboring field oxide isolation regions such that the height of the conductive polysilicon material extends above the topology topography of the field oxide isolation regions; depositing a layer of conductive silicide material superjacent and coextensive the conductive polysilicon material; and then patterning the planarized conductive polysilicon material and the conductive silicide material thereby forming the planarized transistor gate.

What is claimed is:  
     
       1. A process for providing a planarized conductor on a non-planar starting substrate, said process comprising the steps of: 
       forming a layer of planarized conductive material overlying neighboring isolation regions such that the height of said planarized conductive material layer extends above the topology  topography of said neighboring isolation regions;  
       forming a layer of reflective material superjacent and coextensive said planarized conductive material layer; and  
       patterning said planarized conductive material layer thereby forming said planarized conductor.  
     
     
       2. The process of claim  1 , wherein said layer of reflective material comprises a layer of reflective conductive material. 
     
     
       3. The process of claim  1 , wherein said layer of reflective material comprises a layer of partially reflective insulative material. 
     
     
       4. The process of claim  1 , wherein said layer of planarized conductive material is planarized by chemical mechanical polishing. 
     
     
       5. The process of claim  1 , wherein said layer of planarized conductive material comprises conductively doped polysilicon. 
     
     
       6. The process of claim  2 , wherein said layer of reflective conductive material comprises a material selected from the a group of metal silicides and metals. 
     
     
       7. The process of claim  6 , wherein said metal silicides comprise the a group of tungsten silicide and titanium silicide. 
     
     
       8. The process of claim  3 , wherein said layer of partially reflective insulating material comprises nitride. 
     
     
       9. A process for providing a planarized transistor gate on a non-planar starting substrate, said process comprising the steps of: 
       forming a layer of planarized conductive material overlying neighboring isolation regions such that the height of said planarized conductive material layer extends above the topology  topography of said neighboring isolation regions;  
       forming a layer of reflective material superjacent and coextensive said planarized conductive material layer; and  
       patterning said planarized conductive material layer thereby forming said thereby forming said planarized transistor gate.  
     
     
       10. The process of claim  9 , wherein said layer of reflective material comprises reflective conductive material. 
     
     
       11. The process of claim  9 , wherein said reflective material comprises a layer of partially reflective insulative material. 
     
     
       12. The process of claim  9 , wherein said layer of planarized conductive material is planarized by chemical mechanical polishing. 
     
     
       13. The process of claim  9 , wherein said layer of planarized conductive material comprises conductively doped polysilicon. 
     
     
       14. The process of claim  10 , wherein said layer of reflective conductive material comprises a material selected from the a group of metal silicides and metals. 
     
     
       15. The process of claim  14 , wherein said metal silicides comprise the a group of tungsten silicide and titanium silicide. 
     
     
       16. The process of claim  11 , wherein said partially reflective insulating material comprises nitride. 
     
     
       17. The process of claim  9 , wherein said layer of planarized conductive material comprises in-situ conductively doped polysilicon. 
     
     
       18. The process of claim  9 , wherein said layer of planarized conductive polysilicon material is approximately 3000 Å thick. 
     
     
       19. The process of claim  9 , wherein said layer of planarized conductive polysilicon material has a thickness of approximately 1000 Å overlying said field oxide. 
     
     
       20. A process for providing a conductor on a non- planar substrate comprising:    
         forming a layer of conductive material on said non - planar substrate such that the height of said layer of conductive material extends above the topography of said non - planar substrate;    
       
         planarizing said conductive material layer;  
       
       
         forming a layer of at least partially reflective material over said planarized conductive material layer; and  
       
       
         patterning said planarized conductive material layer. 
       
     
     
       21. The process of claim  20 , wherein forming said layer of at least partially reflective material comprises forming a layer of at least partially reflective conductive material. 
     
     
       22. The process of claim  20 , wherein forming said layer of at least partially reflective material comprises forming a layer of at least partially reflective insulating material. 
     
     
       23. The process of claim  22 , wherein forming said layer of at least partially reflective insulative material comprises forming a layer of material having nitride. 
     
     
       24. The process of claim  20 , wherein planarizing said conductive material layer includes abrading said conductive material layer. 
     
     
       25. The process of claim  24 , wherein planarizing said conductive material layer includes chemical mechanical polishing of said conductive material layer. 
     
     
       26. The process of claim  20 , wherein said forming said conductive material layer includes forming a layer of material having conductively doped polysilicon. 
     
     
       27. The process of claim  20 , wherein forming said conductive material layer comprises forming a single layer of said conductive material layer. 
     
     
       28. The process of claim  21 , wherein forming said layer of at least partially reflective conductive material comprises forming a layer of material selected from a group of metal silicides and metals. 
     
     
       29. The process of claim  28 , wherein forming a layer of said metal silicides comprises forming a layer of material selected from a group of tungsten silicide and titanium silicide. 
     
     
       30. A process for providing a transistor gate on a non- planar substrate, said process comprising the steps of:    
         forming a layer of conductive material on said non - planar substrate such that the height of said layer of conductive material extends above the topography of said non - planar substrate;    
       
         planarizing said conductive material layer;  
       
       
         forming a layer of at least partially reflective material over said planarized conductive material layer; and  
       
       
         patterning said planarized conductive material layer. 
       
     
     
       31. The process of claim  30 , wherein forming said layer of at least partially reflective material comprises forming a layer of at least partially reflective conductive material. 
     
     
       32. The process of claim  30 , wherein forming said layer of at least partially reflective material comprises forming a layer of at least partially reflective insulative material. 
     
     
       33. The process of claim  32 , wherein forming said layer of at least partially reflective insulative material comprises forming a layer of material having nitride. 
     
     
       34. The process of claim  30 , wherein planarizing said conductive material layer includes abrading said conductive material layer. 
     
     
       35. The process of claim  34 , wherein planarizing said conductive material layer includes chemical mechanical polishing of said conductive material layer. 
     
     
       36. The process of claim  30 , wherein forming said conductive material layer includes forming a layer of material having conductively doped polysilicon. 
     
     
       37. The process of claim  30 , wherein forming said conductive material layer comprises forming a single layer of said conductive material layer. 
     
     
       38. The process of claim  31 , wherein forming said layer of at least partially reflective conductive material comprises forming a layer of material selected from a group of metal silicides and metals. 
     
     
       39. The process of claim  38 , wherein forming said layer of metal silicides comprises forming a layer of material selected from a group of tungsten silicide and titanium silicide. 
     
     
       40. The process of claim  30 , wherein forming said conductive material layer comprises forming a layer of in- situ conductively doped polysilicon.   
     
     
       41. The process of claim  30 , wherein forming said conductive material layer comprises forming a layer of conductive material having a thickness of approximately  3000  Å. 
     
     
       42. The process of claim  30 , wherein forming said conductive material layer comprises forming a layer of conductive material having a thickness of approximately  1000  Å above the topography of said non- planar substrate.   
     
     
       43. A process for providing a conductor on a non- planar substrate comprising:    
         forming a substantially planar layer of conductive material on said non - planar substrate such that the height of said substantially planar layer of conductive material extends above the topography of said non - planar substrate;    
       
         forming a layer of at least partially reflective material over said substantially planar conductive material layer; and  
       
       
         patterning said substantially planar conductive material layer. 
       
     
     
       44. The process of claim  43 , wherein forming said layer of at least partially reflective material comprises forming a layer of at least partially reflective, conductive material. 
     
     
       45. The process of claim  43 , wherein forming said layer of at least partially reflective material comprises forming a layer of at least partially reflective, insulative material. 
     
     
       46. The process of claim  45 , wherein forming said layer of at least partially reflective insulative material comprises forming a layer of material having nitride. 
     
     
       47. The process of claim  43 , wherein forming said substantially planar conductive material layer comprises forming a layer of material having conductively doped polysilicon. 
     
     
       48. The process of claim  43 , wherein forming said substantially planar conductive material layer comprises forming a single layer of said substantially planar conductive material layer. 
     
     
       49. The process of claim  44 , wherein forming said layer of at least partially reflective conductive material comprises forming a layer of material selected from a group of metal silicides and metals. 
     
     
       50. The process of claim  49 , wherein forming a layer of said metal silicides comprises forming a layer of material selected form a group of tungsten silicide and titanium silicide. 
     
     
       51. A process for providing a transistor gate on a non- planar substrate, said process comprising the steps of:    
         forming a substantially planar layer of conductive material on said non - planar substrate such that the height of said substantially planar layer of conductive material extends above the topography of said non - planar substrate;    
       
         forming a layer of at least partially reflective material over said substantially planar conductive material layer; and  
       
       
         patterning said substantially planar conductive material layer. 
       
     
     
       52. The process of claim  51 , wherein forming said layer of at least partially reflective material comprises forming a layer of at least partially reflective conductive material. 
     
     
       53. The process of claim  51 , wherein forming said layer of at least partially reflective material comprises forming a layer of at least partially reflective insulative material. 
     
     
       54. The process of claim  53 , wherein forming said layer of at least partially reflective insulative material comprises forming a layer of material having nitride. 
     
     
       55. The process of claim  51 , wherein said substantially planar conductive material layer comprises forming a layer of material having conductively doped polysilicon. 
     
     
       56. The process of claim  51 , wherein forming said substantially planar conductive material comprises forming a single layer of said substantially planar conductive material layer. 
     
     
       57. The process of claim  52 , wherein forming said at least partially reflective conductive material layer comprises forming a layer of material selected from a group of metal silicides and metals. 
     
     
       58. The process of claim  57 , wherein forming said metal silicides comprises forming a layer of material selected from a group of tungsten silicide and titanium silicide. 
     
     
       59. The process of claim  51 , wherein forming said substantially planar conductive material layer comprises forming a layer of in- situ conductively doped polysilicon.   
     
     
       60. The process of claim  51 , wherein forming said substantially planar conductive material layer comprises forming a layer of conductive material having a thickness of approximately  3000  Å. 
     
     
       61. The process of claim  51 , wherein forming said substantially planar conductive material layer comprises forming a layer of conductive material having a thickness of approximately  1000  Å above the topography of said non- planar substrate.