Method of multi-level storage in DRAM and apparatus thereof

Abstract

A method of processing data having one of four voltage levels stored in a DRAM cell is comprised of sensing whether or not the data voltage is above or below a voltage level midway between a highest and a lowest of the four levels, setting the voltage on a reference line higher than the lowest and lower than the next highest of the four levels in the event the data voltage is below the midway voltage level, and setting the voltage on the reference line higher than the second highest and lower than the highest of the four levels in the event the data voltage is above the midway point, and sensing whether the data voltage is higher or lower than the reference line, whereby which of the four levels the data occupies is read.

I claim:  
     
       1. A method of processing data having one of four voltage levels stored in a DRAM cell comprising: 
       ( a )  dumping a charge stored in the DRAM cell onto sub - bitlines of a pair of bitlines to provide a sensing voltage of one of four sensing voltage levels on the sub - bitlines;    
       (a  b) sensing whether or not the data  the sensing voltage is above or below a voltage level midway between a highest and a lowest of said four sensing voltage levels,  
       (b  c) setting the voltage, on a reference line  sub- bitline of the pair of bit lines,  higher than the lowest and lower than the next highest of said four sensing voltage levels in the event the data  sensing voltage is below said midway voltage level, and setting the voltage on the reference line  sub- bitline  higher than the second highest and lower than the highest of said four sensing voltage levels in the event the data  sensing voltage is above said midway voltage level, and  
       (c  d) sensing whether the data  sensing voltage is higher or lower than the voltage on the reference line  sub- bitline , whereby which of the four levels the data occupies is read.  
     
     
       2. A method as defined in claim  1  in which the voltage on the reference line  sub- bitline  is set at approximately one half the voltage difference between either of the lowest or highest sensing voltage level and the adjacent one of the four sensing voltage levels. 
     
     
       3. A method as defined in claim  1  in which said four sensing voltage levels are at 0, ⅓, ⅔ and 1 times a power supply voltage scaled by the cell to bitline capacitance ratio, and in which the voltage on the reference line in step (b)  sub- bitline in step  ( c ) is set at either ⅙ or ⅚ the power supply voltage in step (b)  scaled by the cell to bitline capacitance ratio. 
     
     
       4. A method as defined in claim  1  including charging a dummy capacitor to a level representing whether or not said data is above or below said midway voltage, and setting the voltage on the reference line  sub- bitline  by establishing a voltage level thereon which is midway between the highest and lowest of said four sensing voltage levels, then raising or lowering the voltage level thereon by dumping the charge from said dummy capacitor thereon. 
     
     
       5. A method of processing data having one of plural levels stored in a DRAM cell capacitor comprising: 
       (a) dumping the charge of the cell capacitor on a first conductor of a pair of conductors of a folded bitline,  
       (b) maintaining the other conductor of said pair of conductors split into other sub-bitline conductors and charging each of said other sub-bitline conductors to an intermediate voltage,  
       (c) splitting said first of said pair of conductors into first sub-bitline conductors,  
       (d) sensing one of said sub-bitline conductors to determine whether the charge of said cell has a higher voltage than the intermediate voltage of one of said other sub-line conductors and providing a logic level result signal,  
       (e) storing said logic level result signal in a dummy cell capacitor,  
       (f) setting a charge storage capacitor and all of the sub-bitlines, other than a first sub-bitline conductor on which the charges  charge of the cell capacitor was dumped, at to  a predetermined voltage,  
       (g) dumping charge stored in the dummy cell capacitor on said sub-bitlines  sub- bitline  conductors other than the first sub-bitline conductor to which the charge of the cell capacitor was dumped, and on said charge storage capacitor together, thereby varying the predetermined voltage stored thereon to a degree related to the capacitance of said dummy cell capacitor, said charge storage capacitor and said predetermined voltage, to a level above or below the intermediate level,  
       (h) isolating the sub-bitlines,  
       (i) applying said intermediate voltage to one of said other sub-bitline conductors,  
       (j) comparing the cell voltage on one sub-bitline with the voltage on said other sub-bitline carrying said level above or below the intermediate level to obtain a first logic bit, and comparing the voltages carried by the other sub-bitlines to obtain a second logic bit,  
       whereby said first and second logic bits are indicative of one of four states corresponding to one of said plural levels stored in the DRAM cell.  
     
     
       6. A method as defined in claim  5  in which said intermediate and said predetermined voltages are the same. 
     
     
       7. A method as defined in claim  6  in which said intermediate and predetermined voltages are the same midpoint voltage between a highest and lowest voltage state representative of four logical states. 
     
     
       8. A method as defined in claim  3 , including the further steps of short circuiting two or three of the sub-bitlines to share charge thereon and establish a common voltage level, and storing said shared charge corresponding to the common voltage level on said cell, whereby a restore or write operation results. 
     
     
       9. A method as defined in claim  7 , including the further steps of writing logic voltage levels to each of the sub-bitline conductors, short circuiting two or three of the sub-bitlines to share charge thereon and establish a common voltage level, and storing said shared charge corresponding to the common voltage level on said cell, whereby a write operation results. 
     
     
       10. A method as claimed in claim  1  wherein the voltage on the reference sub- bitline is set by charging a capacitor to a level depending on the results of step  ( b )  and discharging the capacitor onto the reference sub - bitline.    
     
     
       11. A method as claimed in claim  10  wherein the capacitor is discharged onto three sub- bitlines including the reference sub - bitline.    
     
     
       12. A method as claimed in claim  1  including charging a capacitor to a level representing whether or not said sensing voltage is above or below said midway voltage, setting the voltage on the reference sub- bitline by establishing a voltage level thereon which is midway between the highest and lowest of said four sensing voltage levels and then raising or lowering the voltage level thereon by dumping the charge from said capacitor thereon.    
     
     
       13. A method as claimed in claim  1  wherein the sensing steps ( b )  and  ( d )  are by sensing amplifiers coupled to opposite ends of the pair of bitlines.    
     
     
       14. A method as claimed in claim  13  wherein the sense amplifiers are disconnected from the pair of bitlines during steps ( a )  and  ( c ) .    
     
     
       15. A method of reading data having one of plural voltage levels stored in a DRAM cell comprising: 
         dumping a stored voltage from the DRAM cell to sub - bitlines which are disconnected from sense amplifiers;    
         in a first sense amplifier, sensing the dumped stored voltage on a first sub - bitline relative to a first reference voltage to define a first bit of a multibit representation of the stored data;    
         dumping a voltage, the level of which is dependent on the value of the first bit, onto a second sub - bitline disconnected from the sense amplifiers to provide a second reference voltage; and    
         in a second sense amplifier, sensing the dumped stored voltage on a third sub - bitline relative to the second reference voltage to define a second bit of said multibit representation of the stored data.    
     
     
       16. A method as claimed in claim  15  wherein one of four voltage levels is stored in the DRAM cell and each of a pair of bitlines is formed of two sub- bitlines.    
     
     
       17. A method as claimed in claim  16  wherein the voltage, the level of which is dependent on the value of the first bit, is dumped onto three sub- bitlines of the pair of bitlines.    
     
     
       18. A method as claimed in claim  17  in which said four levels are at  0 , {fraction ( 1 / 3 )}, {fraction ( 2 / 3 )} and  1  times a power supply voltage scaled by the cell to bitline capacitance ratio, and in which the second reference voltage is set at either {fraction ( 1 / 6 )} or {fraction ( 5 / 6 )} the power supply voltage scaled by the cell to bitline capacitance ratio.  
     
     
       19. A method as claimed in claim  15  wherein a sense amplifier is coupled at each end of a pair of bitlines which are divided into sub- bitlines.    
     
     
       20. A method as claimed in claim  15  wherein the step of dumping a voltage to provide a second reference voltage comprises charging a capacitor to a level representing the first bit, setting the voltage on sub- bitlines by establishing a voltage level thereon which is midway between the highest and lowest of four levels and then raising or lowering the voltage level on the sub - bitline by dumping the charge from said capacitor thereon.    
     
     
       21. A method as claimed in claim  15  wherein the stored voltage from the DRAM cell is dumped onto sub- bitlines of a single pair of bitlines with a sense amplifier coupled to each end thereof.    
     
     
       22. A method of processing data having one of plural voltage levels stored in a DRAM cell comprising: 
         dumping a charged stored in the DRAM cell onto sub - bitlines of a pair of bitlines to provide a sensing voltage of one of plural sensing voltage levels on the sub - bitline;    
       
         sensing whether the sensing voltage is above or below a voltage level midway between a highest and a lowest of said plural levels,  
       
         setting the voltage, on a reference sub - bitline of the pair of bitlines, to a level which is dependent on whether the sensing voltage is sensed to be above or below the midway voltage level; and    
         sensing whether the sensing voltage is higher or lower than the voltage on the reference sub - bitline.    
     
     
       23. A method as claimed in claim  22  wherein the voltage on the reference sub- bitline is set by charging a capacitor to a level which depends on whether the sensing voltage is above or below said voltage level midway between the highest and lowest of said plural levels, and discharging the capacitor onto the reference sub - bitline.    
     
     
       24. A method as claimed in claim  23  wherein the capacitor is discharged onto three sub- bitlines including the reference sub - bitline.    
     
     
       25. A method as claimed in claim  22  wherein the sensing steps are by sensing amplifiers coupled to opposite ends of the pair of bitlines.  
     
     
       26. A method as claimed in claim  25  wherein the sense amplifiers are disconnected from the pair of bitlines during the steps of dumping a charge and setting the voltage.  
     
     
       27. A method as claimed in claim  22  wherein one of four voltage levels is stored in the DRAM cell.  
     
     
       28. A method as claimed in claim  27  wherein the step of setting the voltage includes charging a capacitor to a level representing whether or not said sensing voltage is above or below said midway voltage, setting the voltage on the reference sub- bitline by establishing a voltage level thereon which is midway between the highest and lowest of said plural levels, and then raising or lowering the voltage level thereon by dumping the charge from said capacitor thereon.    
     
     
       29. A method of processing data having one of plural voltage levels stored in a DRAM cell comprising: 
         dumping the voltage stored in said DRAM cell onto sub - bitlines of a pair of bitlines to provide a sensing voltage;    
         sensing the sensing voltage on one of the sub - bitlines relative to a first reference level to provide a first bit;    
         dumping a charge, the level of which depends on the value of the first bit, onto a sub - bitline to establish a second reference level; and    
         sensing whether the sensing voltage on another of the sub - bitlines is above or below the second reference level to provide a second bit.    
     
     
       30. A method as claimed in claim  29  wherein the sensing steps are by sensing amplifiers coupled to opposite ends of the pair of bitlines.  
     
     
       31. A method as claimed in claim  30  wherein the sense amplifiers are disconnected from the pair of bitlines during the steps of dumping.  
     
     
       32. A method as claimed in claim  29  wherein one of four voltage levels is stored in the DRAM cell and each of a pair of bitlines is formed of two sub- bitlines.    
     
     
       33. A method as claimed in claim  32  wherein the charge which depends on the value of the first bit is dumped onto three sub- bitlines of the pair of bitlines.    
     
     
       34. In a DRAM having plural cell capacitors coupled to a pair of conductors of a folded bitline, a method of processing data having one of plural levels stored in one of said cell capacitors comprising: 
       
         dumping the charge of said one of said cell capacitors on a first conductor of the pair of conductors of the folded bitline;  
       
         splitting said first of said pair of conductors into first sub - bitline conductors;    
         charging a sub - bitline of a second conductor of said pair of conductors to an intermediate voltage;    
         sensing one of said first sub-bitline conductors to determine whether the dumped charge has a higher voltage than the intermediate voltage on said sub - bitline of the second conductor and providing a first logic level result signal;    
       
         storing said first logic level result signal in one of said cell capacitors;  
       
         dumping the stored first logic level result signal onto sub - bitline conductors to vary the voltage stored thereon to a degree relating to the capacities of the cell capacitor from which the second first logic level result signal is being dumped and relating to the sub - bitlines, to a level above or below the intermediate voltage; and    
         comparing the cell voltage on another of the first sub - bitline conductors against the level above or below the intermediate voltage to obtain a second logic level result signal.    
     
     
       35. A method of processing data having one of plural voltage levels stored in a DRAM cell comprising: 
         providing a pair of bitlines having a sense amplifier connected at each end thereof, the bitlines being formed of sub - bitlines, the DRAM cell being connected to only one of the sub - bitlines;    
         with the sense amplifiers disconnected from the bitlines, dumping the voltage stored in the DRAM cell onto two sub - bitlines of the pair of bitlines to provide a sensing voltage level;    
         with one of the sensing amplifiers, sensing the sensing voltage on one of the sub - bitlines relative to a first reference level on another sub - bitline to provide a first bit;    
         with the sense amplifiers disconnected from the bitlines, dumping a charge which depends on the value of the first bit onto three sub - bitlines of the pair of bitlines to establish a second reference level; and    
         with the other of the sensing amplifiers, sensing whether the sensing voltage on another of the sub - bitlines is above or below the second reference level to provide a second bit.    
     
     
       36. A dynamic random access memory comprising: 
       
         an array of DRAM cells, each comprising a storage capacitor and a transistor for charging the capacitor from or discharging the capacitor to a single bitline of a pair of bitlines, and a plurality of word lines for enabling the transistors of the DRAM cells;  
       
       
         means for sensing whether a sensing voltage on a bitline, discharged from the data voltage stored on a DRAM cell capacitor, is above or below a first reference level;  
       
       
         means for setting the voltage on a reference line to a level which is dependent on whether the sensing voltage is sensed to be above or below the first reference level; and  
       
       
         means for sensing whether the sensing voltage is higher or lower than a second reference level.  
       
     
     
       37. A dynamic random access memory as claimed in claim  36  wherein pairs of bitlines are coupled to sense amplifiers at opposite ends thereof and the bitlines are divided into sub- bitlines.    
     
     
       38. A dynamic random access memory as claimed in claim  37  wherein each bitline is divided into two sub- bitlines.    
     
     
       39. A dynamic random access memory comprising: 
       
         means for discharging a stored voltage from a DRAM cell to a single bitline of a pair of bitlines;  
       
         means for splitting the bitlines into sub - bitlines;    
         means for comparing the voltage on a sub - bitline to a first reference voltage to define a first bit of a multibit representation of a plural voltage level;    
       
         means for setting a second reference voltage, the level of which is dependent on the value of the first bit; and  
       
         means for comparing the voltage on a second sub - bitline to the second reference voltage to define a second bit of said multibit representation of the plural voltage levels.    
     
     
       40. A dynamic random access memory as claimed in claim  39  wherein pairs of bitlines are coupled to sense amplifiers at opposite ends thereof and the bitlines are divided into sub- bitlines.    
     
     
       41. A dynamic random access memory as claimed in claim  40  wherein each bitline is divided into two sub- bitlines.