Disk reproduction apparatus capable of continuously varying a reproduction speed

Abstract

A pickup reads data recorded on a disk and outputs a current signal corresponding to the read data. An amplifier outputs the current signal as a voltage signal. A data slice circuit binarizes the voltage signal and converts it into an EFM signal. In response to the EFM signal, a PLL circuit generates a PLL clock signal in synchronization with a reproduction speed. When a reference speed or its two-times higher speed is selected as the reproduction speed, if the PLL clock signal is synchronized with the EFM signal, the frequency of the PLL clock signal is proportionate to the reproduction speed. In response to the PLL clock signal, the data slice circuit controls the frequency band of a reference voltage in accordance with the reproduction speed, and outputs the EFM signal. A data processing circuit demodulates the EFM signal and removes a jitter from the demodulated signal in response to the PLL clock signal. The data processing circuit also corrects an error of data corresponding to the demodulated signal in response to the PLL clock signal, and outputs audio data.

What is claimed is: 
     
       1. A disk reproduction apparatus comprising: photoelectric transducer means for optically reading data recorded on a disk and converting the data into an electrical signal;   an amplifier for amplifying the electrical signal supplied from said photoelectric transducer means;   a data slice circuit for binarizing an electrical signal supplied from said amplifier to generate an EFM (eight to fourteen modulation) signal;   a PLL circuit for generating a clock signal corresponding to a variation in reproduction speed of data, in response to the EFM signal supplied from said data slice circuit; and   a data processing circuit for demodulating the EFM signal supplied from said data slice circuit in response to the clock signal supplied from said PLL circuit, and reproducing data,   said data slice circuit including: a comparator for comparing the electrical signal supplied from said amplifier with a reference voltage, said comparator outputting one of data "0" and data "1" in accordance with the electrical signal and the reference voltage;   a frequency divider for dividing a frequency of the clock signal supplied from said PLL circuit to generate a count clock signal;   an up-down counter for counting the count clock signal supplied from said frequency divider in accordance with a time period of the data "0" and a time period of the data "1" supplied from said comparator, said up-down counter outputting differential data representing a difference between the time period of the data "0" and the time period of the data "1"; and     a digital-to-analog convener supplied with the differential data from said up-down counter, said digital-to-analog converter converting the differential data into an analog voltage and supplying the analog voltage to said comparator as the reference voltage.   
     
     
       2. A disk reproduction apparatus according to claim 1, wherein said data processing circuit comprises: a first demodulator for demodulating the EFM signal supplied from said data slice circuit;   a memory for storing data output from said first demodulator;   a controller for writing the data output from said first demodulator to the memory in response to the clock signal supplied from said PLL circuit, and reading out the data written to the memory in response to the clock signal; and   an error correction circuit for correcting an error of the data read out from said controller, in response to the clock signal supplied from said PLL circuit.   
     
     
       3. A disk reproduction apparatus according to claim 2, further comprising a second demodulator for demodulating the data output from said first demodulator into subcode data. 
     
     
       4. A disk reproduction apparatus comprising: photoelectric transducer means for optically reading data recorded on a disk and converting the data into an electrical signal;   a data slice circuit for binarizing the electrical signal supplied from said photoelectric transducer to generate an EFM signal;   a PLL circuit for generating a clock signal corresponding to a variation in reproduction speed of data, in response to the EFM signal supplied from said data slice circuit; and   a data processing circuit for demodulating the EFM signal supplied from said data slice circuit in response to the clock signal supplied from said PLL circuit, and reproducing data,   said data slice circuit including: a first clock signal generator for generating a clock signal in response to the clock signal supplied from said PLL circuit;   a second clock signal generator for generating a clock signal in response to a reference clock signal generated by a quartz oscillator;   a switch connected to said first and second clock signal generators, for selecting one of the clock signals output from said first and second clock signal generators;   a comparator for comparing the electrical signal supplied from said photoelectric transducer with a reference voltage, said comparator outputting one of data "0" and data "1" in accordance with the electrical signal and the reference voltage;   an up-down counter for counting the clock signal selected by said switch in accordance with a time period of the data "0" and a time period of the data "1" supplied from said comparator, said up-down counter outputting differential data representing a difference between the time period of the data "0" and the time period of the data "1"; and   a digital-to-analog converter supplied with the differential data from said up-down counter, said digital-to-analog converter converting the differential data into an analog voltage and supplying the analog voltage to said comparator as the reference voltage.     
     
     
       5. A disk reproduction apparatus according to claim 4, wherein said data processing circuit comprises: a first demodulator for demodulating the EFM signal supplied from said data slice circuit;   a memory for storing data output from said first demodulator;   a controller for writing the data output from said first demodulator to the memory in response to the clock signal supplied from said PLL circuit, and reading out the data written to the memory in response to the clock signal; and   an error correction circuit for correcting an error of the data read out from said controller, in response to the clock signal supplied from said PLL circuit.   
     
     
       6. A disk reproduction apparatus according to claim 5, further comprising a second demodulator for demodulating the data output from said first demodulator into subcode data. 
     
     
       7. A disk reproduction apparatus according to claim 4, wherein said first clock signal generator includes a first frequency divider for dividing a frequency of the clock signal supplied from said PLL circuit and said second clock signal generator includes a second frequency divider for dividing a frequency of the reference clock signal generated by the quartz crystal. 
     
     
       8. A disk reproduction apparatus comprising: photoelectric transducer means for optically reading data recorded on a disk and converting the data into an electrical signal;   a data slice circuit for binarizing the electrical signal supplied from said photoelectric traducer to generate an EFM signal;   a PLL circuit for generating a clock signal corresponding to a variation in reproduction speed of data, in response to the EFM signal supplied from said data slice circuit; and   a data processing circuit for demodulating the EFM signal supplied from said data slice circuit in response to the clock signal supplied from said PLL circuit, and reproducing data,   said data slice circuit including: a comparator for comparing the electrical signal supplied from said photoelectric transducer with a reference voltage, said comparator outputting one of data "0" and data "1" in accordance with the electrical signal and the reference voltage;   a detecting means for detecting differential data representing a difference between the time period of the data "0" and the time period of the data "1" based on the clock signal supplied from said PLL circuit; and   a voltage generating means supplied with the differential data from said detecting means, said voltage generating means for generating a voltage in response to the differential data and supplying the voltage to said comparator as the reference voltage.     
     
     
       9. A disk reproduction apparatus according to claim 8, wherein said data processing circuit comprises: a first demodulator for demodulating the EFM signal supplied from said data slice circuit;   a memory for storing data output from said first demodulator;   a controller for writing the data output from said first demodulator to the memory in response to the clock signal supplied from said PLL circuit, and reading out the data written to the memory in response to the clock signal; and   an error correction circuit for correcting an error of the data read out from said controller, in response to the clock signal supplied from said PLL circuit.   
     
     
       10. A disk reproduction apparatus according to claim 9, further comprising a second demodulator for demodulating the data output from said first demodulator into subcode data. 
     
     
       11. A disk reproduction apparatus comprising: read means for reading data recorded on a disk as an electrical signal;   a data slice circuit for binarizing the electrical signal supplied from said read means to generate an EFM signal;   a PLL circuit for generating a clock signal corresponding to a variation in reproduction speed of data, in response to the EFM signal supplied from said data slice circuit; and   a data processing circuit for demodulating the EFM signal supplied from said data slice circuit in response to the clock signal supplied from said PLL circuit, and reproducing data,   said data slice circuit including: a comparator for comparing the electrical signal read from the disk with a reference voltage, said comparator outputting one of data "0" and data "1" in accordance with the electrical signal and the reference voltage;   an up-down counter for counting the clock signal supplied from said PLL circuit in accordance with a time period of the data "0" and a time period of the data "1" supplied from said comparator, said up-down counter outputting differential data representing a difference between the time period of the data "0" and the time period of the data "1"; and   a digital-to-analog converter supplied with the differential data from said up-down counter, said digital-to-analog converter converting the differential data into an analog voltage and supplying the analog voltage to said comparator as the reference voltage.     
     
     
       12. A disk reproduction apparatus according to claim 11, wherein said data processing circuit comprises: a first demodulator for demodulating the EFM signal supplied from said data slice circuit;   a memory for storing data output from said first demodulator;   a controller for writing the data output from said first demodulator to the memory in response to the clock signal supplied from said PLL circuit, and reading out the data written to the memory in response to the clock signal; and   an error correction circuit for correcting an error of the data read out from said controller, in response to the clock signal supplied from said PLL circuit.   
     
     
       13. A disk reproduction apparatus according to claim 12, further comprising a second demodulator for demodulating the data output from said fast demodulator into subcode data. 
     
     
       14. A disk reproduction apparatus comprising: read means for reading data recorded on a disk as an electrical signal;   a data slice circuit for binarizing the electrical signal supplied from said read means to generate an EFM signal;   a PLL circuit for generating a clock signal corresponding to a variation in reproduction speed of data, in response to the EFM signal supplied from said data slice circuit; and   a data processing circuit for demodulating the EFM signal supplied from said data slice circuit in response to the clock signal supplied from said PLL circuit, and reproducing data,   said data processing circuit including: a first demodulator for demodulating the EFM signal supplied from said data slice circuit;   a memory for storing data output from said first demodulator,   a controller for writing the data output from said first demodulator to the memory in response to the clock signal supplied from said PLL circuit, and reading out the data written to the memory in response to the clock signal; and   an error correction circuit for correcting an error of the data read out from said controller, in response to the clock signal supplied from said PLL circuit, and     said data slice circuit including: a comparator for comparing the electrical signal read from the disk with a reference voltage, said comparator outputting one of data "0" and data "1" in accordance with the electrical signal and the reference voltage;   an up-down counter for counting the clock signal supplied from said PLL circuit in accordance with a time period of the data "0" and a time period of the data "1" supplied from said comparator, said up-down counter outputting differential data representing a difference between the time period of the data "0" and the time period of the data "1"; and   a digital-to-analog converter supplied with the differential data from said up-down counter, said digital-to-analog converter converting the differential data into an analog voltage and supplying the analog voltage to said comparator as the reference voltage.     
     
     
       15. A signal processing circuit for use in disk data reproduction, the disk data being read from a disk and being converted into an amplified electrical signal, the signal processing circuit comprising: a data slice circuit for binarizing the amplified electrical signal to generate a modulated signal; and   a PLL circuit for generating a PLL clock signal corresponding to a variation in reproduction speed of data, in response to the modulated signal supplied from said data slice circuit,   wherein said data slice circuit includes:   a comparator for comparing the amplified electrical signal with a reference voltage, said comparator outputting one of data "0" and data "1" in accordance with the amplified electrical signal and the reference voltage;   a frequency divider for dividing a frequency of the PLL clock signal supplied from said PLL circuit to generate a count clock signal;   an up-down counter for counting the count clock signal supplied from said frequency divider in accordance with a first time period of the data "0" and a second time period of the data "1" supplied from said comparator, said up-down counter outputting differential data representing a difference between the first time is period of the data "0" and the second time period of the data "1"; and   a digital-to-analog converter supplied with the differential data from said up-down counter, said digital-to-analog converter converting the differential data into an analog voltage and supplying the analog voltage to said comparator as the reference voltage,   whereby the data slice circuit binarizes the amplified electrical signal in accordance with the variation in reproduction speed of data.   
     
     
       16. The signal processing circuit according to claim 15, further comprising a data processing circuit for demodulating said modulated signal supplied from said data slice circuit in response to the PLL clock signal supplied from said PLL circuit, and for reproducing data. 
     
     
       17. The signal processing circuit according to claim 16, wherein said data processing circuit comprises: a first demodulator for demodulating signal supplied from said data slice circuit;   a memory for storing data output from said first demodulator;   a controller for writing the data output from said first demodulator to the memory in response to the PLL clock signal supplied from said PLL circuit, and for reading out the data written to the memory in response to the PLL clock signal; and   an error correction circuit for correcting an error of the data read out from said controller, in response to the PLL clock signal supplied from said PLL circuit.   
     
     
       18. The signal processing circuit according to claim 17, further comprising a second demodulator for demodulating the data output from said first demodulator into subcode data. 
     
     
       19. A signal processing circuit for use in disk data reproduction, the disk data being read from a disk and being converted into an amplified electrical signal, the signal processing circuit comprising: a data slice circuit for binarizing the amplified electrical signal to generate a modulated signal; and   a PLL circuit for generating a PLL clock signal corresponding to a variation in reproduction speed of data, in response to the modulated signal supplied from said data slice circuit,   wherein said data slice circuit includes:   a comparator for comparing the amplified electrical signal with a reference voltage, said comparator outputting one of data "0" and data "1" in accordance with the amplified electrical signal and the reference voltage;   a first frequency divider for dividing a frequency of the PLL clock signal supplied from said PLL circuit and for generating a first clock signal;   a second frequency divider for dividing a frequency of a reference clock signal supplied from a quartz oscillator and for outputting a second clock signal;   a switch connected to said first and second frequency dividers, for selecting one of the first and second clock signals and for outputting a count clock signal;   an up-down counter for counting the count clock signal supplied from said switch in accordance with a first time period of the data "0" and a second time period of the data "1" supplied from said comparator, said up-down counter outputting differential data representing a difference between the first time period of the data "0" and the second time period of the data "1"; and   a digital-to-analog converter supplied with the differential data from said up-down counter, said digital-to-analog converter converting the differential data into an analog voltage and supplying the analog voltage to said comparator as the reference voltage,   whereby the data slice circuit binarizes the amplified electrical signal in accordance with the variation in reproduction speed of data.   
     
     
       20. The signal processing circuit according to claim 19, wherein said switch is controlled by a control signal representing whether said PLL circuit is locked or not. 
     
     
       21. The signal processing circuit according to claim 20, wherein said switch selects the first clock signal when said control signal represents a lock state of said PLL circuit, and said switch selects the second clock signal when said control signal represents an unlock state of said PLL circuit. 
     
     
       22. The signal processing circuit according to claim 20, wherein said switch selects the first clock signal output from said PLL circuit when a frequency of the PLL clock signal falls within a predetermined frequency range of said modulated signal, and said switch selects the second clock signal when the frequency of the PLL clock signal falls outside the predetermined frequency range of said modulated signal. 
     
     
       23. The signal processing circuit according to claim 19, further comprising a data processing circuit for demodulating said modulated signal supplied from said data slice circuit in response to the PLL clock signal supplied from said PLL circuit, and for reproducing data. 
     
     
       24. The signal processing circuit according to claim 23, wherein said data processing circuit comprises: a first demodulator for demodulating the modulated signal supplied from said data slice circuit;   a memory for storing data output from said first demodulator,   a controller for writing the data output from said first demodulator to the memory in response to the PLL clock signal supplied from said PLL circuit, and for reading out the data written to the memory in response to the PLL clock signal; and   an error correction circuit for correcting an error of the data read out from said controller, in response to the PLL clock signal supplied from said PLL circuit.   
     
     
       25. The signal processing circuit according to claim 24, further comprising a second demodulator for demodulating the data output from said first demodulator into subcode data. .Iadd. 
     
     
       26.  A disk reproduction apparatus according to one of claims 1-7 and 11-14, wherein the data slice circuit comprises a feedback loop comprising the comparator, the up-down counter, and the digital-to-analog converter and an open loop gain of the feed back loop changes in accordance with changes in the reproduction speed..Iaddend..Iadd.27. A disk reproduction apparatus according to one of claims 8-10, wherein the data slice circuit includes a feedback loop comprising the comparator, the detecting means, and the voltage generating means and an open loop gain of the feed back loop changes in accordance with changes in the reproduction speed..Iaddend..Iadd.28. A signal processing circuit for receiving an electrical signal responsive to a disk data read from a disk, the signal processing circuit comprising a data slice circuit configured to compare the electrical signal with a reference signal and to generate a binarized modulated signal, the data slice circuit including a feedback loop; and   a clock generator configured to generate a clock signal synchronized to a reproduction speed in accordance with the binarized modulated signal,   wherein the data slice circuit is operably coupled to the clock generator, and   wherein an open loop gain of the feedback loop continuously changes in accordance with the reproduction speed..Iaddend..Iadd.29. A signal processing circuit for receiving a reproduction signal derived from disk data read at a reproduction speed from a rotating disk, comprising:   .Iadd.a data slice circuit configured to compare the reproduction signal with a reference signal and to generate a binarized modulated signal, the data slice circuit including a feedback loop; and   .Iadd.a clock generator configured to receive the binarized modulated signal and to generate a clock signal synchronized to the reproduction speed in accordance with the binarized modulated signal;   .Iadd.wherein the feedback loop comprises, .Iadd.a comparator having a first input for receiving the electrical signal, a second input and an output which outputs the binarized modulated signal; and   an integrator configured to receive the binarized modulated signal and the clock signal, to integrate the binarized modulated signal in synchronism with the clock signal, and to feed an integration result to the second     
     
     
        input of the comparator..Iaddend..Iadd.30.  A signal processing method for receiving a reproduction signal responsive to disk data read at a reproduction speed from a rotating disk, comprising: comparing the reproduction signal to a reference signal to produce a data slice output signal having one of first and second logic levels; and   generating said reference signal in synchronism with said reproduction speed as a differential signal indicative of a difference between time periods when said data slice output signal has said first and second logic levels..Iaddend..Iadd.31. A signal processing method according to claim 30, wherein said generating step comprises:   generating said reference signal in a control frequency band which changes continuously in accordance with the reproduction speed..Iaddend..Iadd.32. A signal processing method according to claim 30, wherein said generating step comprises:   generating said reference signal using a feedback loop having an open loop gain which changes in accordance with changes in the reproduction   
     
     
        speed..Iaddend..Iadd.33.  A signal processing method according to claim 32, wherein said generating step comprises: integrating said data slice output signal at a rate synchronized to said reproduction speed..Iaddend..Iadd.34. A signal processing method according to claim 33, wherein said integrating step comprises:   clocking an up/down counter clocked with a clock which varies in accordance with changes in said reproduction speed..Iaddend..Iadd.35. A signal processing method according to claim 34, comprising:   generating said clock based on said data slice output signal and proportionate to said reproduction speed..Iaddend..Iadd.36. A signal processing method according to claim 33, wherein said integrating step comprises:   clocking an up/down counter; and   changing a transmission gain of said counter in accordance with changes in said reproduction speed..Iaddend..Iadd.37. A signal processing circuit for receiving a disk data reproduction signal responsive to disk data read at a reproduction speed from a rotating disk, comprising:   a comparison mechanism configured to compare the disk data reproduction signal to a reference signal and to produce a data slice output signal having one of first and second logic levels; and   a reference signal generation mechanism configured to generate said reference signal in synchronism with said reproduction speed as a differential signal indicative of a difference between time periods when said data slice output signal has said first and second logic   
     
     
        levels..Iaddend..Iadd.38.  A signal processing circuit according to claim 37, wherein said reference signal generation mechanism is configured to generate said reference signal in a control frequency band which changes continuously in accordance with the reproduction speed..Iaddend..Iadd.39. A signal processing circuit according to claim 37, wherein said reference signal generation mechanism comprises: a feedback loop connected to said comparison mechanism and having an open loop gain which changes in accordance with changes in the reproduction speed..Iaddend..Iadd.40. A signal processing circuit according to claim 39, wherein said feedback loop comprises:   an integration circuit which integrates said data slice output signal at a rate synchronized to said reproduction speed..Iaddend..Iadd.41. A signal processing circuit according to claim 40, wherein said integration circuit comprises:   an up/down counter clocked with a clock which varies in accordance with changes in said reproduction speed..Iaddend..Iadd.42. A signal processing circuit according to claim 41, comprising:   a phase lock loop circuit which generates said clock in synchronism with said data slice output signal and proportionate to said reproduction   
     
     
        speed..Iaddend..Iadd.43.  A signal processing circuit according to claim 40, wherein said integration circuit comprises: an up/down counter having a transmission gain which varies in accordance with changes in said reproduction speed..Iaddend..Iadd.44. A signal processing circuit for receiving a disk data reproduction signal responsive to disk data read at a reproduction speed from a rotating disk, comprising:   comparison means for comparing the disk data reproduction signal to a reference signal and producing a data slice output signal having one of first and second logic levels; and   reference signal generation means for generating said reference signal in synchronism with said reproduction speed as a differential signal indicative of a difference between time periods when said data slice output signal has said first and second logic levels..Iaddend..Iadd.45. A signal processing circuit according to claim 44, wherein said reference signal generation means comprises means for generating said reference signal in a control frequency band which changes continuously in accordance with the reproduction speed..Iaddend..Iadd.46. A signal processing circuit according to claim 44, wherein said reference signal generation means comprises:   a feedback loop connected to said comparison means and having an open loop gain which changes in accordance with changes in the reproduction speed..Iaddend..Iadd.47. A signal processing circuit according to claim 46, wherein said feedback loop comprises:   integration means for integrating said data slice output signal at a rate   
     
     
        synchronized to said reproduction speed..Iaddend..Iadd.48.  A signal processing circuit according to claim 47, wherein said integration means comprises: an up/down counter clocked with a clock which varies in accordance with changes in said reproduction speed..Iaddend..Iadd.49. A signal processing circuit according to claim 48, comprising:   a phase lock loop circuit which generates said clock in synchronism with said data slice output signal and proportionate to said reproduction speed..Iaddend..Iadd.50. A signal processing circuit according to claim 47, wherein said integration circuit comprises:   an up/down counter having a transmission gain which varies in accordance with changes in said reproduction speed..Iaddend..Iadd.51. A signal processing method for receiving a reproduction signal responsive to disk data read at a reproduction speed from a rotating disk, comprising:   comparing the reproduction signal to a reference signal to produce a data slice output signal having one of first and second logic levels;   generating a first clock using a phase lock loop having said data slice output signal as an input such that said first clock is synchronized to the reproduction speed;   generating a second clock from a fixed frequency source; and   generating said reference signal using said first clock when said phase lock loop is in a locked condition and using said second clock when said   
     
     
        phase lock loop is in an unlocked condition..Iaddend..Iadd.52.  A signal processing method according to claim 51, wherein said step of generating said reference signal comprises: generating said reference signal in a control frequency band which changes continuously in accordance with the reproduction speed..Iaddend..Iadd.53. A signal processing method according to claim 51, wherein said step of generating said reference signal comprises:   using a feedback loop having an open loop gain which changes in accordance with changes in the reproduction speed when using said first clock and which is constant when using said second clock..Iaddend..Iadd.54. A signal processing method according to claim 53, wherein said step of generating said reference signal comprises:   integrating said data slice output signal at a rate synchronized to said reproduction speed when using said first clock and at a constant rate when using said second clock..Iaddend..Iadd.55. A signal processing method according to claim 54, wherein said integrating step comprises:   clocking an up/down counter clocked with said first clock which varies in accordance with changes in said reproduction speed when said phase lock loop is in a locked condition and with said second clock when said phase lock loop is in an unlocked condition..Iaddend..Iadd.56. A signal processing method according to claim 54, wherein said integrating step comprises:   clocking an up/down counter; and   changing a transmission gain of said counter in accordance with changes in   
     
     
        said reproduction speed..Iaddend..Iadd.57.  A signal processing circuit for receiving a disk data reproduction signal responsive to disk data read at a reproduction speed from a rotating disk, comprising: a comparison mechanism configured to compare the disk data reproduction signal to a reference signal and to produce a data slice output signal having one of first and second logic levels;   a phase lock loop having said data slice output signal as an input and generating a first clock synchronized to the reproduction speed;   a fixed frequency source configured to generate a second clock at a fixed frequency; and   a processor which determines whether said phase lock loop is in a locked condition or in an unlocked condition and selects said first clock for use in generation of said reference signal when said phase lock loop is in a locked condition and selects said second clock for use in generation of said reference signal when said phase lock loop is in an unlocked condition..Iaddend..Iadd.58. A signal processing circuit according to claim 57, comprising:   a feedback loop including said comparison mechanism, said feedback loop having applied thereto said first clock when said phase lock loop is in said locked condition and then having an open loop gain which changes in accordance with changes in the reproduction speed, and said feedback loop having applied thereto said second clock when said phase lock loop is in said unlocked condition and then having a constant open loop   
     
     
        gain..Iaddend..Iadd.59.  A signal processing circuit according to claim 58, wherein said feedback loop comprises: an integrator configured to integrate said data slice output signal at a rate synchronized to said reproduction speed upon application of said first clock and at a constant rate upon application of said second clock..Iaddend..Iadd.60. A signal processing circuit according to claim 59, wherein said integrator comprises:   an up/down counter clocked with said first clock which varies in accordance with changes in said reproduction speed when said phase lock loop is in a locked condition and with said second clock when said phase lock loop is in an unlocked condition..Iaddend..Iadd.61. A signal processing circuit according to claim 59, wherein said integrator comprises:   an up/down counter having a transmission gain which varies in accordance with changes in said reproduction speed..Iaddend..Iadd.62. A signal processing circuit for receiving a disk data reproduction signal responsive to disk data read at a reproduction speed from a rotating disk, comprising:   comparing means for comparing the disk data reproduction signal to a reference signal and for producing a data slice output signal having one of first and second logic levels,   phase lock loop means having said data slice output signal as an input for generating a first clock synchronized to the reproduction speed;   fixed frequency source means for generating a second clock at a fixed frequency; and   processor means for determining whether said phase lock loop is in a locked condition or in an unlocked condition and selecting said first clock for use in generation of said reference signal when said phase lock loop is in a locked condition and selecting said second clock for use in generation of said reference signal when said phase lock loop is in an unlocked   
     
     
        condition..Iaddend..Iadd.63.  A signal processing circuit according to claim 62, comprising: a feedback loop including said comparing means, said feedback loop having applied thereto said first clock when said phase lock loop means is in said locked condition and then having an open loop gain which changes in accordance with changes in the reproduction speed, and said feedback loop having applied thereto said second clock when said phase lock loop means is in said unlocked condition and then having a constant open loop gain..Iaddend..Iadd.64. A signal processing circuit according to claim 63, wherein said feedback loop comprises:   integrator means for integrating said data slice output signal at a rate synchronized to said reproduction speed upon application of said first clock and at a constant rate upon application of said second clock..Iaddend..Iadd.65. A signal processing circuit according to claim 64, wherein said integrator means comprises:   an up/down counter clocked with said first clock which varies in accordance with changes in said reproduction speed when said phase lock loop is in a locked condition and with said second clock when said phase lock loop is   
     
     
        in an unlocked condition..Iaddend..Iadd.66.  A signal processing circuit according to claim 64, wherein said integrator means comprises: .Iadd.an up/down counter having a transmission gain which varies in accordance with changes in said reproduction speed..Iaddend.