Method and circuit for shortcircuiting data transfer lines and semiconductor memory device having the circuit

Abstract

There is provided a method of controlling data transmission lines of a semiconductor memory device which has a first pair of data transmission lines to which a sense amplifier and memory cells are connected, and a second pair of data transmission lines to which a read circuit and a write circuit are connected at an end of the second pair of the data transmission lines, which is connected to the first pair of data transmission lines via a column gate. The method includes a) shortcircuiting the second pair of data transmission lines for a first period when a read operation is carried out, and b) shortcircuiting the second pair of data transmission lines for a second period when a write operation is carried out, the second period being shorter than the first period.

What is claimed is: 
     
       1. A method of controlling data transmission lines of a semiconductor memory .[.device.]. which has a first pair of data transmission lines to which a sense amplifier and memory cells are connected, and a second pair of data transmission lines to which a read circuit and a write circuit are connected .[.at an end of the second pair of the data transmission lines.]., .Iadd.and .Iaddend.which is connected to the first pair of data transmission lines via a .[.column gate.]. .Iadd.switch.Iaddend., said method comprising: a) shortcircuiting the second pair of data transmission lines for a first period .[.when a read operation is carried out.]. .Iadd.in a read mode.Iaddend.; and   b) shortcircuiting the second pair of data transmission lines for a second period .[.when a write operation is carried out.]. .Iadd.in a write mode.Iaddend., and second period being shorter than the first period.   
     
     
       2. A semiconductor .[.device.]. .Iadd.memory .Iaddend.comprising: memory cells;   a sense amplifier;   a first pair of data transmission lines to which the sense amplifier and .Iadd.the .Iaddend.memory cells are connected;   a second pair of data transmission lines to which a read circuit and a write circuit are connected .[.at an end of the second pair of the data transmission lines.]., .Iadd.and .Iaddend.which is connected to the first pair of data transmission lines via a .[.column gate.]. .Iadd.switch.Iaddend.;   a shortcircuiting element which can shortcircuit the second pair of transmission   a first control circuit which controls the shortcircuiting element so that the second pair of data transmission lines is shortcircuited for a first period .[.when a read operation is carried out.]. .Iadd.in a read mode.Iaddend., and the second pair of data transmission lines is shortcircuited for a second period .[.when a write operation is carried out.]. .Iadd.in the write mode.Iaddend., said second period being shorter than the first period. .[.   
     
     
       3.  The semiconductor memory device as claimed in claim 2, wherein the second pair of data transmission lines comprises: a third pair of data transmission lines to which the first pair of data transmission lines is connected; and   a fourth pair of data transmission lines to which the read circuit and the write circuit are connected, the fourth pair of data transmission lines being coupled to the third pair of data transmission lines via a switch circuit..].   
     
     
       4. The semiconductor memory .[.device.]. as claimed in claim 2, further comprising a precharging circuit which supplies a precharge voltage to the second pair of data transmission lines. 
     
     
       5. The semiconductor memory .[.device.]. as claimed in claim 4, wherein said precharging circuit supplies the precharge voltage to the second pair of data transmission lines while the second pair of data transmission lines is being shortcircuited, and does not supply the precharge voltage thereto when the second pair of data transmission lines is not shortcircuited. 
     
     
       6. The semiconductor memory .[.device.]. as claimed in claim 2, .Iadd.further comprising: a column gate controlled by a first signal, and disposed between the first pair of data transmission lines and the sense amplifier, and .Iaddend.wherein the first control circuit controls the shortcircuiting element so that a timing at which the second pair of data transmission lines .[.is.]. .Iadd.initiates to be .Iaddend.shortcircuited substantially coincides with .[.a.]. .Iadd.an inactivation timing of the .Iaddend.first signal .[.defining an operation timing.]. in the read and write .[.operations.]. .Iadd.modes.Iaddend., and a timing at which the second pair of data transmission lines is released from a shortcircuited state in the write .[.operation.]. .Iadd.mode .Iaddend.is earlier.[., with respect to.]. .Iadd.than an activation timing of .Iaddend.the first signal, .Iadd.and .Iaddend.than a timing at which the second pair of data transmission lines is released from the shortcircuited state in the read .[.operation.]. .Iadd.mode..Iaddend.   
     
     
       7. The semiconductor memory .[.device.]. as claimed in claim 4, wherein the first control circuit controls the shortcircuiting element so that the second pair of data transmission lines is released from a shortcircuited state in the read .[.operation.]. .Iadd.mode .Iaddend.after the second pair of data transmission lines .[.is.]. .Iadd.completes to be .Iaddend.precharged to the precharge voltage. 
     
     
       8. The semiconductor memory .[.device.]. as claimed in claim 4, wherein the first control circuit controls the shortcircuiting element so that the second pair of data transmission lines is released from a shortcircuited state in the write .[.operation.]. .Iadd.mode .Iaddend.before the second pair of data transmission lines .[.is.]. .Iadd.completes to be .Iaddend.precharged to the precharge voltage. 
     
     
       9. The semiconductor memory .[.device.]. as claimed in claim 8, wherein said write circuit has a driving capability of setting the second pair of data transmission lines to the precharge voltage .[.faster.]..Iadd., when the write circuit inverts complementary signals on the second pair of data transmission lines larger .Iaddend.than .Iadd.driving capability of .Iaddend.the precharging circuit .[.precharges.]. .Iadd.precharging .Iaddend.the second pair of data transmission lines to the precharge voltage .[.when the write circuit inverts complementary signal on the second pair of data transmission lines.].. 
     
     
       10. The semiconductor memory .[.device.]. as claimed in claim 2, wherein said first control circuit comprises: a second control circuit which controls timings at which the second pair of data transmission lines is .[.shortcircuited and.]. released from a shortcircuited state in the write .[.operation.]. .Iadd.mode.Iaddend.;   a third control circuit which controls timings at which the second pair of data transmission lines is shortcircuited and released from the shortcircuited state in the read .[.operation.]. .Iadd.mode.Iaddend.; and   a fourth control circuit which controls a timing at which the shortcircuiting element shortcircuits .Iadd.and releases from the shortcircuited state of .Iaddend.the second pair of data transmission lines .[.on the basis of.]. .Iadd.in response to .Iaddend.output signals of the second and third control circuits.   
     
     
       11. The semiconductor memory .[.device.]. as claimed in claim 10, wherein: the second control circuit comprises a first NAND circuit which .[.performs a NAND operation on.]. .Iadd.receives .Iaddend.a .[.first.]. .Iadd.second .Iaddend.signal defining an operation timing and a .[.second.]. .Iadd.third .Iaddend.signal indicating .[.whether an operation mode of the semiconductor memory device is.]. the write .[.operation.]. .Iadd.mode .Iaddend.or the read .[.operation.]. .Iadd.mode.Iaddend.;   the third control circuit comprises a first delay circuit delaying the .[.first.]. .Iadd.second .Iaddend.signal, and a second NAND circuit .[.performing a NAND operation.]. .Iadd.receiving .Iaddend.an output signal of the first delay circuit and the .[.first.]. .Iadd.second .Iaddend.signal; and   the fourth control circuit comprises a third NAND circuit .[.performing a NAND operation on.]. .Iadd.receiving .Iaddend.an output signal of the second control circuit and an output signal of the third control circuit, and a first inverting delay circuit which inverts and delays an output signal of the third NAND circuit.   
     
     
       12. The semiconductor memory .[.device.]. as claimed in claim 11, wherein the .[.first.]. .Iadd.second .Iaddend.signal is a signal synchronized with an external clock applied to the semiconductor memory .[.device.].. 
     
     
       13. The semiconductor memory .[.device.]. as claimed in claim 2, further comprising a .[.second.]. .Iadd.fifth .Iaddend.control circuit which .[.controls enabling of.]. .Iadd.activates .Iaddend.the write circuit which outputs data to the second pair of data transmission lines at almost the same time as the second pair of data transmission lines is released from a shortcircuited state. 
     
     
       14. The semiconductor memory .[.device.]. as claimed in claim 13, wherein said .[.second.]. .Iadd.fifth .Iaddend.control circuit controls the write circuit .[.on the basis of.]. .Iadd.in response to .Iaddend.a .[.first.]. .Iadd.second .Iaddend.signal defining an operation timing and a .[.second.]. .Iadd.third .Iaddend.signal indicating .[.whether an operation mode of the semiconductor memory device is.]. the write .[.operation.]. .Iadd.mode .Iaddend.or the read .[.operation.]. .Iadd.mode.Iaddend.. 
     
     
       15. The semiconductor memory .[.device.]. as claimed in claim 14, wherein said .[.second.]. .Iadd.fifth .Iaddend.control circuit comprises: a first inverting circuit which inverts the .[.first.]. .Iadd.second .Iaddend.signal;   a second inverting circuit which inverts the .[.second.]. .Iadd.third .Iaddend.signal;   a first NOR circuit which .[.performs a NOR operation on.]. .Iadd.receives .Iaddend.output signals of the first and second inverting circuits; and   a .[.first.]. .Iadd.second .Iaddend.delay circuit which delays an output signal of the first NOR circuit.   
     
     
       16. The semiconductor memory .[.device.]. as claimed in claim 2, further comprising a .[.second.]. .Iadd.sixth .Iaddend.control circuit which .[.controls enabling of.]. .Iadd.activates .Iaddend.the .[.write.]. .Iadd.read .Iaddend.circuit .[.on the basis of.]. .Iadd.in response to .Iaddend.a .[.first.]. .Iadd.second .Iaddend.signal defining an operation timing and a .[.second.]. .Iadd.third .Iaddend.signal indicating .[.whether an operation mode of the semiconductor memory device is.]. the write .[.operation.]. .Iadd.mode .Iaddend.or the read .[.operation.]. .Iadd.mode.Iaddend.. 
     
     
       17. The semiconductor memory .[.device.]. as claimed in claim 16, wherein said .[.second.]. .Iadd.sixth .Iaddend.control circuit comprises: a .[.first.]. .Iadd.third .Iaddend.inverting circuit which inverts the .[.first.]. .Iadd.second .Iaddend.signal;   a .[.first.]. .Iadd.second .Iaddend.NOR circuit which .[.performs a NOR operation on.]. .Iadd.receives .Iaddend.an output signal of the .[.first.]. .Iadd.third .Iaddend.inverting circuit and the .[.second.]. .Iadd.third .Iaddend.signal; and   a .[.first.]. .Iadd.third .Iaddend.delay circuit which delays an output signal of the .[.first.]. .Iadd.second .Iaddend.NOR circuit.   
     
     
       18. The semiconductor memory .[.device.]. as claimed in claim 6, further comprising a .[.second.]. .Iadd.seventh .Iaddend.control circuit which delays the .[.first.]. .Iadd.second .Iaddend.signal to generate .[.a third.]. .Iadd.the first .Iaddend.signal used to control .[.timings at which the column gate is selected and released from a selected state at respective timings.]. .Iadd.the column gate.Iaddend., which are .[.common to.]. .Iadd.commonly used in .Iaddend.the read .[.operation.]. .Iadd.mode .Iaddend.and the write .[.operation.]. .Iadd.mode.Iaddend.. 
     
     
       19. The semiconductor memory .[.device.]. as claimed in claim 2, further comprising: .Iadd.a column gate controlled by a first signal, and disposed between the first pair of data transmission lines and the sense amplifier;.Iaddend.   .[.a second.]. .Iadd.an eighth .Iaddend.control circuit which controls timings at which .[.a column.]. .Iadd.the first signal .Iaddend.is .[.selected and released from a selected state.]. .Iadd.outputted to the column gate .Iaddend.in the read and write .[.operations.]. .Iadd.modes.Iaddend.; and   a .[.third.]. .Iadd.ninth .Iaddend.control circuit which .[.controls timings at which the column gate is selected and released from the selected state,.]. .Iadd.is coupled to the eighth control circuit, for outputting the first signal.Iaddend.;   wherein .[.the.]. .Iadd.an activation .Iaddend.timing .[.at which the column gate is selected.]. .Iadd.of the first signal .Iaddend.in the write .[.operation.]. .Iadd.mode .Iaddend.lags behind .[.the.]. .Iadd.an activation .Iaddend.timing .[.at which.]. of the .[.column gate is selected.]. .Iadd.first signal .Iaddend.in the read .[.operation.]. .Iadd.mode .Iaddend.and .[.the.]. .Iadd.an inactivation .Iaddend.timing .[.at which the column gate is released from the selected state.]. .Iadd.of the first signal .Iaddend.in the read .[.operation.]. .Iadd.mode .Iaddend.substantially coincides with .[.the.]. .Iadd.an inactivation .Iaddend.timing .[.at which the column gate is released from the selected state.]. .Iadd.of the first signal .Iaddend.in the write .[.operation.]. .Iadd.mode.Iaddend..   
     
     
       20. The semiconductor memory .[.device.]. as claimed in claim 19, wherein the .[.second.]. .Iadd.eighth .Iaddend.control circuit comprises: a .[.first.]. .Iadd.fourth .Iaddend.inverting circuit which inverts a .[.first.]. .Iadd.second .Iaddend.signal defining an operation timing:   a .[.first.]. .Iadd.second .Iaddend.inverting delay circuit which inverts and delays an output signal of the .[.first.]. .Iadd.fourth .Iaddend.inverting circuit;   a .[.first.]. .Iadd.fourth .Iaddend.NAND circuit which .[.performs a NAND operation on.]. .Iadd.receives .Iaddend.a .[.second.]. .Iadd.third .Iaddend.signal indicating .[.whether an operation mode of the semiconductor memory device is.]. the write .[.operation.]. .Iadd.mode .Iaddend.or the read .[.operation.]. .Iadd.mode .Iaddend.and .[.an.]. .Iadd.the .Iaddend.output signal of the .[.first.]. .Iadd.fourth .Iaddend.inverting circuit; and   a .[.first.]. .Iadd.fourth .Iaddend.delay circuit which delays an output signal of the .[.first.]. .Iadd.fourth .Iaddend.NAND circuit; and   wherein the .[.third.]. .Iadd.ninth .Iaddend.control circuit comprises:   a .[.second.]. .Iadd.fifth .Iaddend.NAND circuit which .[.performs a NAND operation on.]. .Iadd.receives .Iaddend.an output signal of the .[.first.]. .Iadd.second .Iaddend.inverting delay circuit and an output signal of the .[.first.]. .Iadd.fourth .Iaddend.delay circuit; and   a .[.second.]. .Iadd.fifth .Iaddend.inverting circuit which inverts an output signal of the .[.second.]. .Iadd.fifth .Iaddend.NAND circuit.   
     
     
       21. The semiconductor memory .[.device.]. as claimed in claim 2, further comprising: .Iadd.a column gate controlled by a first signal, and disposed between the first pair of data transmission lines and the sense amplifier;.Iaddend.   a .[.second.]. .Iadd.tenth .Iaddend.control circuit which controls timings at which .[.a column.]. .Iadd.the first signal .Iaddend.is .[.selected and released from a selected state.]. .Iadd.outputting to the column gate .Iaddend.in the read .[.operation.]. .Iadd.mode.Iaddend.;   .[.a third.]. .Iadd.an eleventh .Iaddend.control circuit which controls timing at which .[.a column is selected and released from the selected state.]. .Iadd.the first signal is outputted to the column gate .Iaddend.in the write .[.operation.]. .Iadd.mode.Iaddend.;   a .[.fourth.]. .Iadd.twelfth .Iaddend.control circuit which generates .[., from.]. .Iadd.the first signal in response to .Iaddend.output signals of the .[.second.]. .Iadd.tenth .Iaddend.and .[.third.]. .Iadd.eleventh .Iaddend.control circuits .[., a third signal which controls timings at which the column gate is selected and released from the selected state.].; and   a .[.fifth.]. .Iadd.thirteenth .Iaddend.control circuit which controls the .[.second.]. .Iadd.tenth .Iaddend.control circuit,   wherein .[.the.]. .Iadd.an activation and an inactivation .Iaddend.timings .[.at which the column gate is selected and released from the selected state.]. .Iadd.of the first signal .Iaddend.in the write .[.operation.]. .Iadd.mode .Iaddend.lag behind the .[.timings at which the column gate is selected and released from the selected state.]. .Iadd.activation and the inactivation of the first signal .Iaddend.in the read .[.operation.]. .Iadd.mode, respectively..Iaddend.   
     
     
       22. The semiconductor memory .[.device.]. as claimed in claim 21 wherein said .[.second.]. .Iadd.tenth .Iaddend.control circuit comprises: a .[.first.]. .Iadd.sixth .Iaddend.inverting circuit which inverts a .[.first.]. .Iadd.second .Iaddend.signal defining an operation timing;   a .[.first.]. .Iadd.sixth .Iaddend.NAND circuit which .[.performs a NAND operation on.]. .Iadd.receives .Iaddend.an output signal of the .[.first.]. .Iadd.sixth .Iaddend.inverting circuit and an output signal of the .[.fifth.]. .Iadd.thirteenth .Iaddend.control circuit; and   a .[.first.]. .Iadd.fifth .Iaddend.delay which delays an output signal of the .[.first.]. .Iadd.sixth .Iaddend.NAND circuit,   wherein said .[.third.]. .Iadd.eleventh .Iaddend.control circuit comprises:   a .[.second.]. .Iadd.seventh .Iaddend.NAND circuit which .[.performs a NAND operation on.]. .Iadd.receives .Iaddend.a .[.second.]. .Iadd.third .Iaddend.signal indicating .[.whether an operation mode of the semiconductor memory device is.]. the write .[.operation.]. .Iadd.mode .Iaddend.or the read .[.operation.]. .Iadd.mode .Iaddend.and an output signal of the .[.first.]. .Iadd.sixth .Iaddend.inverting circuit; and   a .[.second.]. .Iadd.sixth .Iaddend.delay circuit which delays an output signal of the .[.second.]. .Iadd.seventh .Iaddend.NAND circuit,   wherein said .[.fourth.]. .Iadd.twelfth .Iaddend. control circuit comprises:   .[.a third.]. .Iadd.an eighth .Iaddend.NAND circuit which .[.performs a NAND operation on.]. .Iadd.receives .Iaddend.output signals of the .[.second.]. .Iadd.tenth .Iaddend.and .[.third.]. .Iadd.eleventh .Iaddend.control circuits; and   a .[.second.]. .Iadd.seventh .Iaddend.inverting circuit which inverts an output signal of the .[.third.]. .Iadd.eighth .Iaddend.NAND circuit, and   wherein said .[.fifth.]. .Iadd.thirteenth .Iaddend.control circuit comprises:   a .[.third.]. .Iadd.seventh .Iaddend.delay circuit which delays the .[.second.]. .Iadd.third .Iaddend.signal; and   a .[.fourth.]. .Iadd.ninth .Iaddend.NAND circuit which .[.performs a NAND operation on.]. .Iadd.receives .Iaddend.an output signal of the .[.third.]. .Iadd.seventh .Iaddend.delay circuit and the .[.second.]. .Iadd.third .Iaddend.signal. .Iadd.   
     
     
       23.  A semiconductor memory having a read mode and a write mode, comprising: a sense amplifier;   a pair of data transmission lines for coupling the sense amplifier and a read circuit or a write circuit;   a shortcircuit switch for shortcircuiting the pair of data transmission lines;   a control circuit receiving a control signal which indicates the read mode or the write mode, for controlling an operation of the shortcircuit switch in response to the control signal;   wherein an OFF timing of the shortcircuit switch in the write mode is different from that in the read mode..Iaddend..Iadd.24. The semiconductor memory as claimed in claim 23, wherein   the OFF timing of the shortcircuit switch in the write mode is earlier than that in the read mode..Iaddend..Iadd.25. The semiconductor memory as claimed in claim 24, the pair of data transmission lines including:   a first pair of data transmission lines coupled to the sense amplifier; and   a second pair of data transmission lines coupled between the first pair of data transmission lines and the write circuit;   wherein the shortcircuit switch is disposed between the second pair of data transmission lines..Iaddend..Iadd.26. The semiconductor memory as claimed in claim 25, wherein the shortcircuit switch is disposed in vicinity of the write circuit..Iaddend..Iadd.27. The semiconductor memory as claimed in claim 25, further comprising:   a precharge circuit for supplying a precharge voltage to the second pair of   
     
     
        data transmission lines..Iaddend..Iadd.28.  The semiconductor memory as claimed in claim 27, wherein the precharge circuit supplies the precharge voltage to the second pair of data transmission lines while the second pair of data transmission lines is being shortcircuited, and does not supply the precharge voltage thereto when the second pair of data transmission lines is not shortcircuited..Iaddend..Iadd.29. The semiconductor memory as claimed in claim 27, wherein   the control circuit turns the shortcircuit switch OFF before both of the second pair of data transmission lines complete to be precharged to the precharge voltage, in the write mode..Iaddend..Iadd.30. The semiconductor memory as claimed in claim 27, wherein   the control circuit turns the shortcircuit switch OFF after both of the second pair of data transmission lines completes to be precharged to the precharge voltage, in the read mode..Iaddend..Iadd.31. The semiconductor memory as claimed in claim 23, further comprising:   a column gate controlled by a column selection signal, for coupling the sense amplifier and the pair of data transmission lines; wherein   the OFF timing of the shortcircuit switch in the read mode is substantially same as an activation timing of the column selection signal, and   an ON timing of the shortcircuit switch in the read mode is substantially same as an inactivation timing of the column selection signal..Iaddend..Iadd.32. The semiconductor memory as claimed in claim 23, further comprising:   a column gate controlled by a column selection signal, for coupling the sense amplifier and the pair of data transmission lines; wherein   the OFF timing of the shortcircuit switch in the write mode is earlier than   
     
     
        an activation timing of the column selection signal..Iaddend..Iadd.33. The semiconductor memory as claimed in claim 32, wherein the OFF timing of the shortcircuit switch in the write mode is substantially same as an activation timing of the write circuit..Iaddend..Iadd.34. The semiconductor memory as claimed in claim 23, further comprising:   a column gate controlled by a column selection signal, for coupling the sense amplifier and the pair of data transmission lines; wherein   an activation timing of the column selection signal in the read mode is earlier than that in the write mode..Iaddend..Iadd.35. The semiconductor memory as claimed in claim 34, wherein   an inactivation timing of the column selection signal in the read mode is earlier than that in the write mode..Iaddend..Iadd.36. A method of controlling data transmission lines of a semiconductor memory having a read mode and a write mode, including a pair of data transmission for coupling a sense amplifier and a read circuit or a write circuit and a shortcircuit switch for shortcircuiting the pair of data transmission lines; said method comprising:   a) turning the shortcircuit switch OFF at a first timing in the read mode;   b) turning the shortcircuit switch OFF at a second timing in the write mode, the second timing being earlier than the first timing..Iaddend..Iadd.37. A semiconductor memory having a read mode and a write mode, comprising:   a sense amplifier;   a pair of data transmission lines for coupling the sense amplifier and a read circuit or a write circuit;   a shortcircuit switch for shortcircuiting the pair of data transmission lines;   a control circuit receiving a control signal which indicates the read mode or the write mode, for controlling an operation of the shortcircuit switch in response to the control signal;   a precharge circuit for supplying a precharge voltage to the pair of data transmission lines;   wherein an OFF timing of the shortcircuit switch in the write mode is earlier than a precharge completion timing of the pair of data transmission lines..Iaddend..Iadd.38. The semiconductor memory as claimed in claim 37, wherein   the OFF timing of the shortcircuit switch is substantially same timing as   
     
     
        an activation timing of the write circuit..Iaddend..Iadd.39.  A semiconductor memory having a read mode and a write mode, comprising: a sense amplifier;   a pair of data transmission lines for coupling the sense amplifier and a read circuit or a write circuit;   a shortcircuit switch receiving a shortcircuit signal for shortcircuiting the pair of data transmission lines; and   a control circuit receiving a timing signal and a control signal which indicates the read mode or the write mode, for outputting the shortcircuit signal in response to the timing signal and the control signal,   wherein the control circuit includes:   a first part receiving the timing signal and the control signal for outputting a second timing signal to control an output timing of the shortcircuit signal in the write mode; and   a second part receiving the timing signal for outputting a third timing signal to control the output timing of the shortcircuit in the read mode..Iaddend..Iadd.40. The semiconductor memory as claimed in claim 39, wherein an OFF timing of the shortcircuit switch in the write mode is earlier than that in the read mode..Iaddend..Iadd.41. The semiconductor memory as claimed in claim 39, wherein a first delay time in the write mode produced by the first part is shorter than a second delay time in the read mode produced by the second part..Iaddend..Iadd.42. The semiconductor memory as claimed in claim 39, the pair of data transmission lines including:   a first pair of data transmission lines coupled to the sense amplifier; and   a second pair of data transmission lines coupled between the first pair of data transmission lines and the write circuit;   wherein the shortcircuit switch is disposed between the second pair of data transmission lines..Iaddend..Iadd.43. The semiconductor memory as claimed in claim 42, further comprising:   a precharge circuit for supplying a precharge voltage to the second pair of data transmission lines..Iaddend..Iadd.44. The semiconductor memory as claimed in claim 43, wherein   the precharge circuit supplies the precharge voltage to the second pair of data transmission lines while the second pair of data transmission lines is being shortcircuited, and does not supply the precharge voltage thereto when the second pair of data transmission lines is not   
     
     
        shortcircuited..Iaddend..Iadd.45.  The semiconductor memory as claimed in claim 44, wherein the control circuit turns the shortcircuit switch OFF before each lines of the second pair of data transmission lines completes to be precharged to the precharge voltage, in the write mode..Iaddend..Iadd.46. The semiconductor memory as claimed in claim 44, wherein   the control circuit turns the shortcircuit switch OFF after each line of the second pair of data transmission lines completes to be precharged to the precharge voltage, in the read mode..Iaddend..Iadd.47. The semiconductor memory as claimed in claim 40, wherein   the OFF timing of the shortcircuit switch in the write mode is substantially same as an activation timing of the write circuit..Iaddend.