Wordline driver circuit having a directly gated pull-down device

Abstract

The invention is a circuit and method for quickly driving non-selected wordlines to correct potentials. The invention drives the non-selected wordlines to low potentials through a driving device directly gated by a primary select predecode signal generated by decode circuitry. The driving device is electrically interposed between the wordline and a reference node. The invention provides low power operation, and provides reliable wordline selection for circuits having supply potentials less than 5 volts.

What is claimed is: 
     
       1. A memory device, comprising: a) an output node;   b) decode circuitry for determining a logic state of said output node, said decode circuitry generating a primary and a secondary predecode signal;   c) a driving circuit for driving the output node to an inactive logic state when actuated, said driving circuit directly actuated by a corresponding primary predecode signal;   d) a latching circuit for monitoring the logic state of the output node and latching the output node to said inactive logic state;   e) an inverter circuit for inverting said primary predecode signal to said output node; and   f) a pass device for transmitting said primary predecode signal to said inverter when actuated by said secondary predecode signal, such that when said driving circuit is deactuated by said primary predecode signal and said pass device is actuated by said secondary predecode signal said wordline is driven to an active logic state.   
     
     
       2. A method for driving a wordline to a potential having an inactive logic state, the method comprising the following steps: a) generating a primary predecode signal having an actuation potential;   b) actuating a driving device with said primary predecode signal having a full value of said actuation potential;   c) driving the wordline to the potential having the inactive logic state through the driving device;   d) generating a latch signal in response to the inactive logic state on the wordline, said latch signal having a potential capable of actuating latch circuitry;   e) actuating said latch circuitry with said latch signal;   f) latching the wordline to the inactive logic state through said latch circuitry;   g) actuating a precharge device with said primary predecode signal having the full value of said actuation potential; and   h) pulling a serial node to a precharge potential through said precharge device. .Iadd.   
     
     
       3.  A memory device, comprising: a) an output node;   b) decode circuitry adapted to generate a primary predecode signal and a secondary predecode signal;   c) a driving circuit directly actuable by said primary predecode signal to drive the output node to an inactive logic state;   d) a latching circuit responsive to the logic state of the output node and adapted to latch the output node to said inactive logic state;   e) an inverter circuit adapted to invert said primary predecode signal to said output node; and   f) a pass device controlled by said secondary predecode signal for selectively transmitting said primary predecode signal to said inverter, such that when said driving circuit is not actuated by said primary predecode signal and said pass device is actuated by said secondary predecode signal said output node is driven to an active logic state..Iaddend..Iadd.4. A method for driving a wordline to a potential having an inactive logic state, comprising:   a) generating a primary predecode signal having an actuation potential;   b) actuating a driving device with said primary predecode signal;   c) driving the wordline to the potential having the inactive logic state through the driving device, said inactive logic state comprising a latch signal having a potential capable of actuating latch circuitry;   d) actuating said latch circuitry with said latch signal;   e) latching the wordline to the inactive logic state through said latch circuitry;   f) actuating a precharge device with said primary predecode signal having the full value of said actuation potential; and   g) pulling a serial node to a precharge potential with said actuated   
     
     
        precharge device..Iaddend..Iadd.5.  A memory device, comprising: a) an output;   b) decode circuitry for generating a primary predecode signal and a secondary predecode signal;   c) a driving circuit directly responsive to said primary predecode signal to drive the output to an inactive logic state;   d) a latching circuit adapted to latch the output to said inactive logic state responsive to such logic state;   e) an inverter circuit adapted to invert said primary predecode signal to said output; and   f) a pass device controlled by said predecode signal for selectively passing said primary predecode signal to said inverter, such that when said driving circuit is not actuated by said primary predecode signal and said pass device is actuated by said secondary predecode signal said output is driven to an active logic state..Iaddend..Iadd.6. A method for driving a wordline to an inactive logic state potential, comprising:   a) generating a primary predecode signal having an actuation potential;   b) generating a secondary predecode signal controlling a pass transistor gating said primary predecode signal to an input of a latch driving the wordline;   c) actuating a driving device with said primary predecode signal;   d) driving the wordline to the inactive logic state potential through the driving device; and   e) latching the wordline to the inactive logic state without regard to the state of the secondary predecode signal..Iaddend..Iadd.7. A memory device, comprising:   a) an output;   b) decode circuitry for generating a primary predecode signal and a secondary predecode signal;   c) a driving circuit directly responsive to said primary predecode signal to drive the output to an inactive logic state; and   d) a pass device controlled by said secondary predecode signal for selectively passing said primary predecode signal, such that when said driving circuit is not actuated by said primary predecode signal and said pass device is actuated by said secondary predecode signal said primary decode signal determines the logic state of the output independently of said driving circuit..Iaddend..Iadd.8. A method for driving a wordline to an inactive logic state potential, comprising:   a) generating a primary predecode signal having an actuation potential;   b) generating at least one secondary predecode signal capable of gating the primary predecode signal to at least one serial node;   c) actuating a driving device with said primary predecode signal;   d) driving the wordline to the inactive logic state potential through the driving device;   e) latching the wordline to the inactive logic state; and   f) actuating a precharge device with said primary predecode signal to pull said at least one serial node to a precharge potential..Iaddend..Iadd.9. A memory device, comprising:   a) a wordline;   b) decode circuitry for generating a primary predecode signal and a secondary predecode signal;   c) a driving circuit directly responsive to said primary predecode signal to drive the wordline to an inactive logic state; and   d) a pass device controlled by said secondary predecode signal for selectively passing said primary predecode signal, such that when said driving circuit is not actuated by said primary predecode signal and said pass device is actuated by said secondary predecode signal said primary decode signal determines the logic state of the output independently of said driving circuit..Iaddend..Iadd.10. A memory device, comprising:   a) a wordline;   b) decode circuitry for generating a primary predecode signal and a secondary predecode signal;   c) a pass device controlled by said secondary predecode signal for selectively passing said primary predecode signal to said wordline;   d) a driving circuit gated by said decode circuitry without control by said pass device to receive said primary predecode signal and drive the   
     
     
        wordline to an inactive logic state responsive thereto..Iaddend..Iadd.11. A memory device circuit, comprising: a) a wordline;   b) decode circuitry for generating a primary predecode signal and a secondary predecode signal; and   c) a driving circuit directly responsive to said primary predecode signal to drive the wordline to an inactive logic state without regard to the state of said secondary predecode signal..Iaddend..Iadd.12. A method for driving a wordline to an inactive logic state potential, comprising:   a) generating a primary predecode signal having an actuation potential;   b) generating a secondary predecode signal controlling a pass transistor gating said primary predecode signal to an input of a latch driving the wordline;   c) pulling the wordline to a low reference potential through a pull-down transistor directly responsive to said primary predecode signal without gating said primary predecode signal to said input of said latch..Iaddend..Iadd.13. In a memory device having one or more conductors for activating memory cells in the memory device, a conductor driver circuit comprising:   inversion circuitry for driving one of the conductors to an active state in response to a primary decode signal of the memory device being in an active state and a secondary select signal of the memory device being in an active state; and   switching circuitry for driving the one of the conductors to an inactive state in response to the secondary select signal being in an inactive state..Iaddend..Iadd.14. The conductor driver circuit of claim 13, wherein the switching circuitry comprises an NMOS transistor..Iaddend..Iadd.15. The conductor driver circuit of claim 13, wherein the inversion circuitry comprises an inverter..Iaddend..Iadd.16. The conductor driver circuit of claim 15, wherein the inverter comprises an NMOS transistor and a PMOS   
     
     
        transistor..Iaddend..Iadd.17.  A wordline driver circuit, comprising: an inverting latch;   a wordline connected to the output of said inverting latch;   a primary decode signal line for carrying a primary decode signal;   a secondary decode signal line for carrying a secondary decode signal;   a pass transistor gated by said secondary decode signal for passing said primary decode signal to the input of said inverting latch; and   a pull-down transistor directly gated by said primary decode signal with output connected to said wordline for deactivating said wordline when said primary decode signal is deactivated..Iaddend..Iadd.18. The wordline driver circuit of claim 17, wherein said inverting latch comprises:   a PMOS transistor having a drain coupled to V ccp , a gate coupled to said wordline and a source coupled to the input of said inverting latch;   an NMOS transistor having a drain coupled to the output of said inverting latch, a gate coupled to the input of said inverting latch and a source coupled to a reference voltage; and   a PMOS transistor having a gate coupled to the input of said inverting latch, a drain coupled to V ccp  and a source coupled to the output of said inverting latch..Iaddend..Iadd.19. The wordline driver circuit of claim 17, further comprising a continuously gated pass transistor between said pass transistor and the input of said inverting latch having a drain coupled to the output of said pass transistor and a source coupled to the   
     
     
        input of said inverting latch..Iaddend..Iadd.20.  The wordline driver circuit of claim 19, wherein said continuously gated pass transistor is an NMOS transistor with a gate coupled to V ccp ..Iaddend..Iadd.21. The wordline driver circuit of claim 19, wherein said inverting latch comprises: a PMOS transistor having a drain coupled to V ccp , a gate coupled to said wordline and a source coupled to the input of said inverting latch;   an NMOS transistor having a drain coupled to the output of said inverting latch, a gate coupled to the node between said pass transistor and said continuously gated pass transistor, and a source coupled to a reference voltage; and   a PMOS transistor having a gate coupled to the input of said inverting latch, a drain coupled to V ccp  and a source coupled to the output of said inverting latch..Iaddend..Iadd.22. A tree decoded wordline driver circuit, comprising:   an inverting latch;   a wordline connected to the output of said inverting latch;   a primary decode signal line for carrying a primary decode signal;   a plurality of secondary decode signal lines for carrying a plurality of secondary decode signals;   a plurality of pass transistors gated by said plurality of secondary decode signals for passing said primary decode signal along a plurality of serial nodes to the input of said inverting latch; and   a pull-down transistor directly gated by said primary decode signal with output connected to said wordline for deactivating said wordline when said primary decode signal is deactivated..Iaddend..Iadd.23. The tree decoded wordline driver circuit of claim 22, further comprising a plurality of precharging transistor circuits each coupled exclusively to one of said plurality of serial nodes for precharging each of said plurality of serial nodes when said primary decode signal is deactivated..Iaddend..Iadd.24. The tree decoded wordline driver circuit of claim 23, wherein each of said plurality of precharging transistor circuits is an NMOS transistor having drain coupled to Vcc, gate coupled to said primary decode signal and source coupled exclusively to one of said plurality of serial nodes..Iaddend.