Insulated gate semiconductor device with stripe widths

Abstract

There is disclosed an insulated gate bipolar transistor which includes a p type semiconductor region (11) formed in a surface of an n - semiconductor layer (3) by double diffusion in corresponding relation to a p type base region (4) of an IGBT cell adjacent thereto, and an emitter electrode (9) formed on and connected to the p type semiconductor region (11) through a contact hole (CH P ) having a width (W ch2 ) which is greater than a width (W ch1 ) of a contact hole (CH 1 ), thereby preventing device breakdown due to latch-up by the operation of a parasitic thyristor during an ON state and during an ON-state to OFF-state transition even if main and control electrodes in an active region are reduced in size.

What is claimed is: 
     
       1. An insulated gate semiconductor device comprising: a first semiconductor layer of a first conductivity type and having a first concentration;   a plurality of stripe-shaped second semiconductor layers of a second conductivity type selectively formed in parallel in a surface of said first semiconductor layer;   a plurality of third semiconductor layers of the first conductivity type and having a second concentration which is relatively higher compared to said first concentration, said third semiconductor layers being selectively formed in respective surfaces of said second semiconductor layers;   a plurality of stripe-shaped insulating layers formed on upper surfaces of said first and second semiconductor layers between ends of said third semiconductor layers in said second semiconductor layers;   a plurality of stripe-shaped control electrodes formed on said insulating layers;   a plurality of layer insulating films covering said control electrodes;   said first semiconductor layer, said second semiconductor layers, said third semiconductor layers, said insulating layers, said control electrodes, and said layer insulating films forming an active region;   a fourth semiconductor layer of the second conductivity type formed in the surface of said first semiconductor layer so as to enclose said active region; and   a plurality of stripe-shaped main electrodes electrically connected to each other, said plurality of main electrodes being classified into first main electrodes formed on upper surfaces of said second and third semiconductor layers which are not covered with said layer insulating films and second main electrodes formed on an upper surface of said fourth semiconductor layer which is not covered with said layer insulating films,   wherein a stripe width of said second main electrodes adjacent said active region is greater than a stripe width of said first main electrodes within said active region; and   said first semiconductor layer has a thickness which is not less than 5 times a distance between centerlines of said control electrodes adjacent to each other.   
     
     
       2. An insulated gate semiconductor device comprising: a first semiconductor layer of a first conductivity type and having a first concentration;   a plurality of strip-shaped second semiconductor layers of a second conductivity type selectively formed in parallel in a surface of said first semiconductor layer;   a plurality of third semiconductor layers of the first conductivity type and having a second concentration which is relatively higher compared to said first concentration, said third semiconductor layers being selectively formed in respective surfaces of said second semiconductor layers;   a plurality of stripe-shaped insulating layers formed on upper surfaces of said first and second semiconductor layers between ends of said third semiconductor layers in said second semiconductor layers;   a plurality of stripe-shaped control electrodes formed on said insulating layers;   a plurality of layer insulating films covering said control electrodes;   said first semiconductor layer, said second semiconductor layers, said third semiconductor layers, said insulating layers, said control electrodes and said layer insulating films forming an active region;   a fourth semiconductor layer of the second conductivity type formed in the surface of said first semiconductor layer so as to enclose said active region; and   a plurality of stripe-shaped main electrodes electrically connected to each other, said plurality of main electrodes being classified into first main electrodes formed on upper surfaces of said second and third semiconductor layers which are not covered with said layer insulating films and second main electrodes formed on an upper surface of said fourth semiconductor layer which is not covered with said layer insulating films,   wherein a stripe width of said second main electrodes adjacent said active region is greater than a stripe width of said first main electrodes within said active region; and   said third semiconductor layers are not formed in said second semiconductor layers adjacent said fourth semiconductor layer.   
     
     
       3. An insulated gate semiconductor device comprising: a first semiconductor layer of a first conductivity type and having a first concentration;   a plurality of stripe-shaped second semiconductor layers of a second conductivity type selectively formed in parallel in a surface of said first semiconductor layer;   a plurality of third semiconductor layers of the first conductivity type and having a second concentration which is relatively higher compared to said first concentration, said third semiconductor layers being selectively formed in respective surfaces of said second semiconductor layers;   A plurality of stripe-shaped insulating layers formed on upper surfaces of said first and second semiconductor layers between ends of said third semiconductor layers in said second semiconductor layers;   a plurality of stripe-shaped control electrodes formed on said insulating layers;   a plurality of layer insulating films covering said control electrodes;   said first semiconductor layer, said second semiconductor layers, said third semiconductor layers, said insulating layers, said control electrodes, and said layer insulating films forming an active region;   a fourth semiconductor layer of the second conductivity type formed in the surface of said first semiconductor layer so as to enclose said active region; and   a plurality of stripe-shaped main electrodes electrically connected to each other, said plurality of main electrodes being classified into first main electrodes formed on upper surfaces of said second and third semiconductor layers which are not covered with said layer insulating films and second main electrodes formed on an upper surface of said fourth semiconductor layer which is not covered with said layer insulating films,   wherein a stripe width of said second main electrodes adjacent said active region is greater than a stripe width of said first main electrodes within said active region; and   a fifth semiconductor layer of the second conductivity type and having a higher concentration then said fourth semiconductor layer, said fifth semiconductor layer being selectively formed in the upper surface of said fourth semiconductor layer to be in contact with said second main electrodes.   
     
     
       4. The insulated gate semiconductor device of claim 3, wherein said first conductivity type is an N type and said second conductivity type is a P type. 
     
     
       5. An insulated gate semiconductor device comprising: a first semiconductor layer of a first conductivity type and having a first concentration;   a plurality of stripe-shaped second semiconductor layers of a second conductivity type selectively formed in parallel in a surface of said first semiconductor layer;   a plurality of third semiconductor layers of the first conductivity type and having a second concentration which is relatively higher compared to said first concentration, said third semiconductor layers being selectively formed in respective surfaces of said second semiconductor layers;   a plurality of insulating films formed on upper surfaces of said third semiconductor layers and on inner wall surfaces of a plurality of stripe-shaped grooves extending from the upper surface of said third semiconductor layers in said second semiconductor layers through said second semiconductor layers into said first semiconductor layer;   a plurality of stripe-shaped control electrodes formed in said grooves having the inner wall surfaces on which said insulating films are formed;   a plurality of layer insulating films covering said control electrodes and said insulating films;   said first semiconductor layer, said second semiconductor layers, said third semiconductor layers, said insulating films, said control electrodes, and said layer insulating films forming an active region;   a fourth semiconductor layer of the second conductivity type formed in the surface of said first semiconductor layer so as to enclose said active region; and   a plurality of stripe-shaped main electrodes electrically connected to each other, said plurality of main electrodes being classified into first main electrodes formed on upper surfaces of said second and third semiconductor layers which are not covered with said layer insulating films and second main electrodes formed on an upper surface of said fourth semiconductor layer which is not covered with said layer insulating films,   wherein a stripe width of said second main electrodes adjacent said active region is greater than a stripe width of said first main electrodes within said active region.   
     
     
       6. The insulated gate semiconductor device of claim 5, wherein said first semiconductor layer has a thickness which is not less than five times a distance between centerlines of said control electrodes adjacent to each other. 
     
     
       7. The insulated gate semiconductor device of claim 5, wherein said third semiconductor layers are not formed in said second semiconductor layers adjacent said fourth semiconductor layer. 
     
     
       8. The insulated gate semiconductor device of claim 5, further comprising: a fifth semiconductor layer of the second conductivity type and having a higher concentration than said fourth semiconductor layer, said fifth semiconductor layer being formed in the upper surface of said fourth semiconductor layer below said second main electrodes.   
     
     
       9. The insulated gate semiconductor device of claim 8, wherein said first conductivity type is an N type and said second conductivity type is a P type. 
     
     
       10. The insulated gate semiconductor device of claim 5, further comprising an additional insulating film and additional control electrode formed on the surface of the fourth semiconductor layer and having the same thickness as said plurality of insulating films and said plurality of stripe-shape control electrodes. 
     
     
       11. The insulated gate semiconductor device of claim 1, wherein said first conductivity type is an N type and said second conductivity type is a P type. 
     
     
       12. The insulated gate semiconductor device of claim 2, wherein said first conductivity type is an N type and said second conductivity type is a P type. .Iadd. 
     
     
       13.  An insulated gate semiconductor device comprising: a first semiconductor layer of a first conductivity type and having a first concentration;   a plurality of stripe-shaped second semiconductor layers of a second conductivity type selectively formed in parallel in a surface of said first semiconductor layer;   a plurality of third semiconductor layers of the first conductivity type and having a second concentration higher than the first concentration, said third semiconductor layers being selectively formed in respective surfaces of said second semiconductor layers;   a plurality of stripe-shaped insulating layers formed on upper surfaces of said first and second semiconductor layers between ends of said third semiconductor layers in said second semiconductor layers;   a plurality of stripe-shaped control electrodes formed on said insulating layers;   a plurality of layer insulating films covering said control electrodes;   said first semiconductor layer, said second semiconductor layers, said third semiconductor layers, said insulating layers, said control electrodes, and said layer insulating films forming an active region;   a fourth semiconductor layer of the second conductivity type formed in the surface of said first semiconductor layer so as to enclose said active region; and   a plurality of stripe-shaped main electrodes electrically connected to each other, said plurality of main electrodes being classified into first main electrodes formed on upper surfaces of said second and third semiconductor layers which are not covered with said layer insulating films and second main electrodes formed on an upper surface of said fourth semiconductor layer which is not covered with said layer insulating films,   wherein said third semiconductor layers are not formed at least in said second semiconductor layers which are adjacent to and in parallel with said fourth semiconductor layers..Iaddend..Iadd.14. The insulated gate semiconductor device of claim 13, wherein said first semiconductor layer has a thickness which is not less than five times a distance between centerlines of said control electrodes adjacent of each   
     
     
        other..Iaddend..Iadd.15.  The insulated gate semiconductor device of claim 13, further comprising: a fifth semiconductor of the second conductivity type and having a concentration higher than said fourth semiconductor layer, said fifth semiconductor layer being formed in the upper surface of said fourth semiconductor layer to be in contact with said second main electrodes..Iaddend..Iadd.16. An insulated gate semiconductor device comprising:   a first semiconductor layer of a first conductivity type and having a first concentration;   a plurality of stripe-shaped second semiconductor layers of a second conductivity type selectively formed in parallel in a surface of said first semiconductor layer;   a plurality of third semiconductor layers of the first conductivity type and having a second concentration higher than the first concentration, said third semiconductor layers being selectively formed in respective surfaces of said second semiconductor layers;   a plurality of insulating films formed on upper surfaces of said third semiconductor layers and on inner wall surfaces of a plurality of stripe-shaped grooves extending from the upper surface of said third semiconductor layers in said second semiconductor layers through said second semiconductor layers into said first semiconductor layer;   a plurality of stripe-shaped control electrodes formed in said grooves having the inner wall surfaces on which said insulating films are formed;   a plurality of layer insulating films covering said control electrodes and said insulating films;   said first semiconductor layer, said second semiconductor layers, said third semiconductor layers, said insulating films, said control electrodes, and said layer insulating films forming an active region;   a fourth semiconductor layer of the second conductivity type formed in the surface of said first semiconductor layer so as to enclose said active region; and   a plurality of stripe-shaped main electrodes electrically connected to each other, said plurality of main electrodes being classified into first main electrodes being classified into first main electrodes formed on upper surfaces of said second and third semiconductor layers which are not covered with said layer insulating films and second main electrodes formed on an upper surface of said fourth semiconductor layer which is not covered with said layer insulating films,   wherein said third semiconductor layers are not formed at least in said second semiconductor layers which are adjacent to and in parallel with said fourth semiconductor layers..Iaddend..Iadd.17. The insulated gate semiconductor device of claim 16, wherein said first semiconductor layer has a thickness which is not less than five times a distance between centerlines of said control electrodes adjacent to each other..Iaddend..Iadd.18. The insulated gate semiconductor device of claim 16, further comprising:   a fifth semiconductor layer of the second conductivity type and having a concentration higher than said fourth semiconductor layer, said fifth semiconductor layer being formed in the upper surface of said fourth semiconductor layer to be in contact with said second main electrodes..Iaddend..Iadd.19. An insulated gate semiconductor device comprising:   a first semiconductor layer of a first conductivity type and having a first concentration;   a plurality of stripe-shaped second semiconductor layers of a second conductivity type selectively formed in parallel in a surface of said first semiconductor layer;   a plurality of third semiconductor layers of the first conductivity type and having a second concentration higher than the first concentration, said third semiconductor layers being selectively formed in respective surfaces of said second semiconductor layers;   a plurality of stripe-shaped insulating layers formed on upper surfaces of said first and second semiconductor layers between ends of said third semiconductor layers in said second semiconductor layers;   a plurality of stripe-shaped control electrodes formed on said insulating layers;   a plurality of layer insulating films covering said control electrodes;   said first semiconductor layer, said second semiconductor layers, said third semiconductor layers, said insulating layers, said control electrodes, and said layer insulating films forming an active region;   a fourth semiconductor layer of the second conductivity type formed in the surface of said first semiconductor layer so as to enclose said active region; and   a plurality of stripe-shaped main electrodes electrically connected to each other, said plurality of main electrodes being classified into first main electrodes formed on upper surfaces of said second and third semiconductor layers which are not covered with said layer insulating films and second main electrodes formed on an upper surface of said fourth semiconductor layer which is not covered with said layer insulating films;   wherein,   said first main electrodes and said second semiconductor layer are connected through a first contact hole,   said second main electrodes and said fourth semiconductor layer are connected through a second contact hole, and   said first and second contact holes are arranged to be independent of each   
     
     
        other..Iaddend..Iadd.20.  The insulated gate semiconductor device of claim 19, wherein a stripe width of said second main electrodes adjacent said active region is greater than a stripe width of said first main electrodes within said active region..Iaddend..Iadd.21. The insulated gate semiconductor device of claim 19, wherein said third semiconductor layers are not formed at least in said second semiconductor layers which are adjacent to and in parallel with said fourth semiconductor layers..Iaddend..Iadd.22. The insulated gate semiconductor device of claim 19, further comprising: a fifth semiconductor layer of the second conductivity type and having a concentration higher than said fourth semiconductor layer, said fifth semiconductor layer being formed in the upper surface of said fourth semiconductor layer to be in contact with said second main electrodes..Iaddend..Iadd.23. An insulated gate semiconductor device comprising:   a first semiconductor layer of a first conductivity type and having a first concentration;   a plurality of stripe-shaped second semiconductor layers of a second conductivity type selectively formed in parallel in a surface of said first semiconductor layer;   a plurality of third semiconductor layers of the first conductivity type and having a second concentration higher than the first concentration, said third semiconductor layers being selectively formed in respective surfaces of said second semiconductor layers;   a plurality of insulating films formed on upper surfaces of said third semiconductor layers and on inner wall surfaces of a plurality of stripe-shaped grooves extending from the upper surface of said third semiconductor layers in said second semiconductor layers through said second semiconductor layers into said first semiconductor layer;   a plurality of stripe-shaped control electrodes formed in said grooves having the inner wall surfaces on which said insulating films are formed;   a plurality of layer insulating films covering said control electrodes and said insulating films;   said first semiconductor layer, said second semiconductor layers, said third semiconductor layers, said insulating films, said control electrodes, and said layer insulating films forming an active region;   a fourth semiconductor layer of the second conductivity type formed in the surface of said first semiconductor layer so as to enclose said active region; and   a plurality of stripe-shaped main electrodes electrically connected to each other, said plurality of main electrodes being classified into first main electrodes formed on upper surfaces of said second and third semiconductor layers which are not covered with said layer insulating films and second main electrodes formed on an upper surface of said fourth semiconductor layer which is not covered with said layer insulating films; wherein   said first main electrodes and at least said second semiconductor layer are connected through a first contact hole,   said second main electrodes and said fourth semiconductor layer are connected through a second contact hole, and   said first and second contact holes are arranged to be independent of each   
     
     
        other..Iaddend..Iadd.24.  The insulated gate semiconductor device of claim 23, wherein a stripe width of said second main electrodes adjacent said active region is greater than a stripe width of said first main electrodes within said active region..Iaddend..Iadd.25. The insulated gate semiconductor device of claim 23, wherein said third semiconductor layers are not formed at least in said second semiconductor layers which are adjacent to and in parallel with said fourth semiconductor 
     
     
        layers..Iaddend..Iadd.26.  The insulated gate semiconductor device of claim 23, further comprising: a fifth semiconductor layer of the second conductivity type and having a concentration higher than said fourth semiconductor layer, said fifth semiconductor layer being formed in the upper surface of said fourth semiconductor layer to in contact with said second main   
     
     
        electrodes..Iaddend..Iadd.27.  An insulated gate semiconductor device composing: a first semiconductor layer of a first conductivity type and having a first concentration;   a plurality of stripe-shaped second semiconductor layers of a second conductivity type selectively formed in parallel in a surface of said first semiconductor layer;   a plurality of third semiconductor layers of the first conductivity type and having a second concentration higher than the first concentration, said third semiconductor layers being selectively formed in respective surfaces of said second semiconductor layers;   a plurality of stripe-shaped insulating layers formed on upper surfaces of said first and second semiconductor layers between ends of said third semiconductor layers in said second semiconductor layers;   a plurality of stripe-shaped control electrodes formed on said insulating layers;   a plurality of layer insulating films covering said control electrodes;   said first semiconductor layer, said second semiconductor layers, said third semiconductor layers, said insulating layers, said control electrodes, and said layer insulating films forming an active region;   a fourth semiconductor layer of the second conductivity type formed in the surface of said first semiconductor layer so as to enclose said active region; and   a plurality of stripe-shaped main electrodes electrically connected to each other,   said plurality of main electrodes including first main electrodes formed on upper surfaces of said second and third semiconductor layers which are not covered with said layer insulating films and second main electrodes formed on an upper surface of said fourth semiconductor layer which is not covered with said layer insulating films,   wherein a stripe width of said second main electrodes adjacent said active region is greater than a stripe width of said first main electrodes within said active region; and   wherein said fourth semiconductor layer has a shallow portion which reaches a first depth, and a deep portion which reaches a second depth deeper than said first depth,   wherein said second main electrodes have parts formed over said shallow portion and said deep portion, and   wherein the area of the part of said second main electrodes which overlaps said deep portion is greater than the area of the part of said second main electrodes which overlaps said shallow portion..Iaddend..Iadd.28. The insulated gate semiconductor device of claim 27, further comprising:   a fifth semiconductor layer of the second conductivity type and having a concentration higher than said fourth semiconductor layer, said fifth semiconductor layer being formed in the upper surface of said fourth semiconductor layer to be in contact with said second main electrodes..Iaddend.