Semiconductor memory device having an improved wiring and decoder arrangement to decrease wiring delay

Abstract

Word lines of a memory cell array are coupled to the output portion of a first decoder while the input portion of the first decoder is coupled to a plurality of signal lines which are elongated on the memory cell array. The signal lines are provided for a predetermined plurality of word lines, and each of said signal lines can be coupled to the word lines by switching devices. Preferably, the signal lines can be formed of a low resistance material such as aluminum to enhance the speed while the word lines can be formed of polycrystalline silicon to allow simultaneous formation with the memory cell gate electrodes. By virtue of providing each signal line for more than one word line, the design requirements for the signal lines are less stringent than previous arrangements wherein a one-to-one relationship has been attempted between polycrystalline silicon word lines and aluminum connection lines. A further feature of the present invention is the use of a second decoder having an output portion coupled to the signal lines and an input portion coupled to receive selection signals for selecting a predetermined one of the signal lines.

I claim: 
     
       1. A semiconductor integrated circuit comprising: .[.a.]. .Iadd.first and second .Iaddend.memory cell .[.array including.]. .Iadd.arrays each of which includes .Iaddend.a plurality of word lines extending in a column direction, a plurality of bit lines extending in a row direction and intersecting with said word lines, and a plurality of .Iadd.dynamic .Iaddend.memory cells disposed in predetermined ones of said intersections between said word lines and said bit lines;   a first .[.decoder.]. .Iadd.circuit .Iaddend.having an output portion connected electrically with said word lines .Iadd.of said first memory cell array;   a second circuit having an output portion connected electrically with said word lines of said second memory cell array.Iaddend.; and   a plurality of signal lines .Iadd.each of which is .Iaddend.elongated on said .Iadd.first and second .Iaddend.memory .[.array.]. .Iadd.cell arrays .Iaddend.and connected electrically with .[.an.]. .Iadd.a first .Iaddend.input portion of .Iadd.each of .Iaddend.said .[.decoder.]. .Iadd.first and second circuits.Iaddend.,   wherein.Iadd., in each of said first and second memory cell arrays, .Iaddend.each of said signal lines is provided for a predetermined number of said word lines greater than or equal to two.Iadd.,   wherein each of said first and second circuits is a decoder and has a second input portion supplied with the same address signals.Iaddend..   
     
     
       2. A semiconductor integrated circuit device as set forth in claim 1, wherein said signal lines are made of a conductive material having a lower sheet resistance than that of said word lines. 
     
     
       3. A semiconductor integrated circuit device as set forth in claim 1, wherein said signal lines are formed on an insulating film over said word lines and extend generally in said column direction. 
     
     
       4. A semiconductor integrated circuit device as set forth in claim 1, wherein .Iadd.each of .Iaddend.said first .[.decoder.]. .Iadd.and second circuits .Iaddend.includes a plurality of switching circuits respectively coupled between each of said signal lines and said corresponding predetermined number of word lines, said switching circuits each being coupled to a selection line providing selection signals to said switching circuits to operate predetermined ones of said switching circuits to couple selected word lines to said signal lines. 
     
     
       5. A semiconductor integrated circuit device comprising: a memory cell array including a plurality of word lines extending in a column direction, a plurality of bit lines extending in a row direction and intersecting with said word lines, and a plurality of memory cells disposed in predetermined ones of said intersections between said word lines and said bit lines;   a first decoder having an output portion connected electrically with said word lines; and   a plurality of signal lines elongated on said memory array and connected electrically with an input portion of said decoder, wherein each of said signal lines is provided for a predetermined number of said word lines greater than or equal to two,   wherein said first decoder includes a plurality of switching circuits respectively coupled between each of said signal lines and said corresponding predetermined number of word lines, said switching circuits each being coupled to a selection line providing selection signals to said switching circuits to operate predetermined ones of said switching circuits to couple selected word lines to said signal lines,   wherein each of said switching circuits includes a switching IGFET and a cutting IGFET having a source and drain connected between a selection line and a gate of said switching IGFET, and wherein said cutting IGFET further includes a gate electrode connected to a reference potential line.   
     
     
       6. A semiconductor integrated circuit device comprising: a memory cell array including a plurality of word lines extending in a column direction, a plurality of bit lines extending in a row direction and intersecting with said word lines, and a plurality of memory cells disposed in predetermined ones of said intersections between said word lines and said bit lines;   a first decoder having an output portion connected electrically with said word lines; and   a plurality of signal lines elongated on said memory array and connected electrically with an input portion of said decoder, wherein each of said signal lines is provided for a predetermined number of said word lines greater than or equal to two,   wherein each said memory cell comprises a storage capacitor and a selection IGFET having a source and drain connected between a bit line and said storage capacitor.   
     
     
       7. A semiconductor integrated circuit device as set forth in claim 1, wherein said word lines are comprises of polycrystalline silicon and said signal lines are comprised of aluminum. 
     
     
       8. A semiconductor integrated circuit device comprising: a memory cell array including a plurality of word lines extending in a column direction, a plurality of bit lines extending in a row direction and intersecting with said word lines, and a plurality of .Iadd.dynamic .Iaddend.memory cells disposed in predetermined ones of said intersections between said word lines and said bit lines;   a first decoder having .Iadd.a first input portion receiving first X-address signals and .Iaddend.an output portion connected electrically with said word lines; and   a plurality of signal lines elongated on said memory .Iadd.cell .Iaddend.array and connected electrically with .[.an.]. .Iadd.a second .Iaddend.input portion of said .Iadd.first .Iaddend.decoder, wherein each of said signal lines is provided for a predetermined number of said word lines greater than or equal to two,   further comprising a second decoder having an output portion coupled to said signal lines and an input portion .[.coupled to receive selection signals.]. .Iadd.receiving second X-address signals .Iaddend.for selecting a predetermined one of said signal lines.Iadd.,   wherein, in conjunction with selection of the predetermined one of said signal lines based on said second X-address signals, one of said word lines corresponding to the selected signal line is selected on the basis of said first X-address signals.Iaddend..   
     
     
       9. A semiconductor integrated circuit device as set forth in claim 8, wherein said first and second decoders are located on opposite sides of said memory cell array with said signal lines extending from the output portion of said second decoder over said memory cell array to said input portion of said first decoder. 
     
     
       10. A semiconductor integrated circuit device as set forth in claim 8, wherein said integrated circuit device includes a plurality of said memory cell arrays arranged in said column direction, and wherein said first decoder is interposed between at least two of said memory cell arrays and wherein said second decoder is located at an end of said plurality of memory cell arrays so that at least one of said memory cell arrays is interposed between said first and second decoders with said signal lines extending over said memory cell array interposed between said first and second decoders. 
     
     
       11. A semiconductor integrated circuit device as set forth in claim 10, wherein said integrated circuit device comprises at least three memory cell arrays and wherein at least two of said first decoders are provided, each of said first decoders being located between a pair of said memory cell arrays and wherein said signal lines extend, in common, from said output portion of said second decoder over said memory cell array to input portions of each of said first decoders. 
     
     
       12. A semiconductor integrated circuit device as set forth in claim 8, wherein said integrated circuit device includes at least two memory cell arrays in said column direction, and wherein said second decoder is located between said two memory cell arrays and further wherein said integrated circuit device includes at least two first decoders located respectively on opposite sides of each of said memory cell arrays so that each memory cell array is interposed between said second decoder and one of said first decoders with said signal lines extending from the output portion of said second decoder over said memory cell arrays to said input portion of each of said first decoders. 
     
     
       13. A semiconductor integrated circuit device as set forth in claim 6, wherein each of said signal lines is comprised of a conductive material having a lower sheet resistance than that of each of said word lines. 
     
     
       14. A semiconductor integrated circuit device as set forth in claim 13, wherein said signal lines are formed on an insulating film over said word lines and extend generally in said column direction. 
     
     
       15. A semiconductor integrated circuit device as set forth in claim 14, wherein each of said word lines is comprised of polycrystalline silicon and each of said signal lines is comprised of aluminum. 
     
     
       16. A semiconductor integrated circuit device as set forth in claim 14, wherein said first decoder includes a plurality of switching circuits respectively coupled between each of said signal lines and said corresponding predetermined number of word lines, said switching circuits each being coupled to a selection line providing selection signals to said switching circuits to operate predetermined ones of said switching circuits to couple selected word lines to said signal lines. 
     
     
       17. A semiconductor integrated circuit device as set forth in claim 8, wherein each said memory cell comprises a storage capacitor and a selection IGFET having a source and drain connected between a bit line and said storage capacitor. 
     
     
       18. A semiconductor integrated circuit device as set forth in claim 17, wherein each of said signal lines is comprised of a conductive material having a lower sheet resistance than that of each of said word lines. 
     
     
       19. A semiconductor integrated circuit device as set forth in claim 18, wherein said signal lines are formed on an insulating film over said word lines and extend generally in said column direction. 
     
     
       20. A semiconductor integrated circuit device as set forth in claim 19, wherein each of said word lines is comprised of polycrystalline silicon and each of said signal lines is comprised of aluminum. 
     
     
       21. A semiconductor integrated circuit device as set forth in claim 19, wherein said first decoder includes a plurality of switching circuits respectively coupled between each of said signal lines and said corresponding predetermined number of word lines, said switching circuits each being coupled to a selection line providing selection signals to said switching circuits to operate predetermined ones of said switching circuits to couple selected word lines to said signal lines. 
     
     
       22. A semiconductor integrated circuit device as set forth in claim 9, wherein each said memory cell comprises a storage capacitor and a selection IGFET having a source and drain connected between a bit line and said storage capacitor. 
     
     
       23. A semiconductor integrated circuit device as set forth in claim 22, wherein each of said signal lines is comprised of a conductive material having a lower sheet resistance than that of each of said word lines. 
     
     
       24. A semiconductor integrated circuit device as set forth in claim 23, wherein said signal lines are formed on an insulating film over said word lines and extend generally in said column direction. 
     
     
       25. A semiconductor integrated circuit device as set forth in claim 24, wherein each of said word lines is comprised of polycrystalline silicon and each of said signal lines is comprised of aluminum. 
     
     
       26. A semiconductor integrated circuit device as set forth in claim 24, wherein said first decoder includes a plurality of switching circuits respectively coupled between each of said signal lines and said corresponding predetermined number of word lines, said switching circuits each being coupled to a selection line providing selection signals to said switching circuits to operate predetermined ones of said switching circuits to couple selected word lines to said signal lines. .Iadd.27. A semiconductor integrated circuit according to claim 1, wherein one of word lines of said first memory cell array and one of word lines of said second memory cell array are simultaneously both in selected states on the basis of a signal from a selected one of said plurality of signal lines and said same address signals applied to the first and second circuits. .Iaddend..Iadd.28. A semiconductor integrated circuit comprising:   first and second memory cell arrays, each of which includes a plurality of word lines extending in a column direction, a plurality of bit lines extending in a row direction and intersecting with said word lines, and a plurality of dynamic memory cells disposed in predetermined one of said intersecting between said word lines and said bit lines;   a decoder having an address input portion and an output portion connected electrically with said word lines of said first and second memory cell arrays; and   a plurality of signal lines, each of which is elongated on said first and second memory cell arrays and connected electrically with an input portion of said decoder,   wherein, in each of said first and second memory cell arrays, each of said signal lines is provided for a predetermined number of said word lines greater than or equal to two,   wherein wires forming word lines of said first memory cell array are separated from wires forming word lines of said second memory cell array,   wherein one of word lines of said first memory cell array is selected on the basis of signals from one of said plurality of signal lines and signals obtained by decoding a first address supplied to said address input portion of said decoder, and   wherein one of word lines of said second memory cell array is selected on the basis of said signals from said one of said plurality of signal lines and signals obtained by decoding the same first address. .Iaddend..Iadd.29. A semiconductor integrated circuit according to claim 28,   wherein one of word lines of said first memory cell array and one of word lines of said second memory cell array are simultaneously both in selected   
     
     
        states. .Iaddend..Iadd.30.  A semiconductor integrated circuit according t claim 8, wherein said first X-address signals and said second X-address signals are row address signals corresponding to a row address strobe signal. .Iaddend..Iadd.31. A semiconductor integrated circuit according to claim 30, further comprising a Y-decoder which selects one of said bit lines on the basis of column address signals corresponding to a column address strobe signal. .Iaddend..Iadd.32. A semiconductor integrated circuit according to claim 1, wherein each of said memory cells comprises a storage capacitor and a selection IGFET having a gate electrode, wherein said signal lines are made of a conductive material having a lower sheet resistance than that of said word lines, wherein said word lines and said gate electrodes are comprised of the same conductive material and are formed simultaneously with one another, and wherein said signal lines are formed on an insulating film over said word lines and said gate   
     
     
        electrodes. .Iaddend..Iadd.33.  A semiconductor integrated circuit according to claim 8, wherein each of said memory cells comprises a storage capacitor and a selection IGFET having a gate electrode, wherein said signal lines are made of a conductive material having a lower sheet resistance than that of said word lines, wherein said word lines and said gate electrodes are comprised of the same conductive material and are formed simultaneously with one another, and wherein said signal lines are formed on an insulating film over said word lines and said gate electrodes. .Iaddend..Iadd.34. A semiconductor integrated circuit according to claim 28, wherein each of said memory cells comprises a storage capacitor and a selection IGFET having a gate electrode, wherein said signal lines are made of a conductive material having a lower sheet resistance than that of said word lines, wherein said word lines and said gate electrodes are comprised of the same conductive material and are formed simultaneously with one another, and wherein said signal lines are formed on an insulating film over said word lines and said gate electrodes. .Iaddend.