Non-volatile memory device with a sense amplifier capable of copying back

Abstract

Disclosed is a non-volatile semiconductor memory device for transferring data which is inverted data of held data onto bit lines, without reading out read data to an external unit, when data is copied back. This device comprises NAND memory cells connected to bit lines, a flip-flop circuit for temporarily holding write data, a P channel transistor for precharging the bit lines to a predetermined potential, an N channel transistor for connecting the bit lines to the flip-flop circuit, and an N channel transistor having both ends connected between a node of the flip-flop circuit on the opposite side to the bit lines and one end of the transistor on the bit line side. The transistor is provided to hold read data and then output a potential according to its inverted data onto the bit lines. The individual terminals of the flip-flop circuit are connected via a column gate to an I/O line and a BI/O line (inverted-signal line of I/O).

What is claimed is: 
     
       1. A non-volatile semiconductor memory device comprising: memory cells each constituted of a transistor having a charge accumulating layer, each of said memory cells storing in write mode data corresponding to a threshold value which changes greatly as an absolute value of a difference between potentials applied to a drain and a gate becomes larger;   bit lines to each of which drains of a plurality of memory cells are commonly connected;   precharge means for precharging said bit lines to a predetermined potential in read mode;   data holding means for temporarily holding data read from said memory cells; and   inverted-data outputting means for outputting a potential corresponding to inversion of said data held in said data holding means, to said bit lines.   
     
     
       2. The non-volatile semiconductor memory device according to claim 1, further comprising verifying means for verifying a writing operation on memory cells done by said inverted-data outputting means, said verifying means including transfer control means for controlling connection between said bit lines to said data holding means, and there is a period for electrically disconnecting said bit lines from said data holding means at a time of a verifying operation. 
     
     
       3. The non-volatile semiconductor memory device according to claim 2, wherein said verifying means includes a first verifying transistor which conducts at a time of said verifying operation and a second verifying transistor whose gate is controlled in accordance with a signal at a predetermined node of said data holding means, whereby said first and second verifying transistors constitute a current path for controlling a potential of said bit lines in accordance with said signal at said predetermined node of said data holding means at a time of said verifying operation. 
     
     
       4. The non-volatile semiconductor memory device according to claim 2, wherein said verifying means includes a first verifying transistor which conducts at a time of said verifying operation and a second verifying transistor whose gate is controlled in accordance with a signal on said bit lines, whereby said first and second verifying transistors constitute a current path for inverting data at a predetermined node of said data holding means when verification is completed. 
     
     
       5. A non-volatile semiconductor memory device comprising: memory cells each constituted of a transistor having a charge accumulating layer, each of said memory cells storing, in write mode, data corresponding to a threshold value which changes greatly as an absolute value of a difference between potentials applied to a drain and a gate becomes larger;   bit lines to each of which drains of a plurality of memory cells are commonly connected;   precharge means, connected to said bit lines, for precharging said bit lines to a predetermined potential in read mode;   bistable data holding means for temporarily holding data read from said memory cells or data to be written in said memory cells;   first transfer control means for connecting said bit lines to one node of said bistable data holding means; and   second transfer control means for connecting said bit lines to the other node of said bistable data holding means.   
     
     
       6. The non-volatile semiconductor memory device according to claim 5, wherein in read mode, said bistable data holding means is previously disabled, and is enabled after said bit lines and said precharge means are set in a free running state to thereby hold data according to a potential of said bit lines then. 
     
     
       7. The non-volatile semiconductor memory device according to claim 6, further comprising a first verifying transistor which conducts at a time of a verifying operation and a second verifying transistor whose gate is controlled in accordance with a signal at said other node of said bistable data holding means, whereby said first and second verifying transistors constitute a current path for controlling a potential of said bit lines in accordance with said signal at said other node of said data holding means at a time of said verifying operation. 
     
     
       8. The non-volatile semiconductor memory device according to claim 6, further comprising a first verifying transistor which conducts at a time of a first verifying operation, a second verifying transistor whose gate is controlled in accordance with a signal at said one node of said bistable data holding means, a third verifying transistor which conducts at a time of a second verifying operation, and a fourth verifying transistor whose gate is controlled in accordance with a signal at said other node of said bistable data holding means, whereby said first and second verifying transistors constitute a first current path for controlling a potential of said bit lines in accordance with said signal at said one node of said data holding means at a time of said first verifying operation and said third and fourth verifying transistors constitute a second current path for controlling a potential of said bit lines in accordance with said signal at said other node of said data holding means at a time of said second verifying operation. 
     
     
       9. The non-volatile semiconductor memory device according to claim 5, wherein in read mode, said bistable data holding means is previously disabled, and data held in said bistable data holding means is inverted or uninverted in accordance with a potential of said bit lines after said precharge means and said bit lines are set in a free running state. 
     
     
       10. The non-volatile semiconductor memory device according to claim 9, wherein said bistable data holding means has reset means. 
     
     
       11. The non-volatile semiconductor memory device according to claim 9, further comprising a first verifying transistor which conducts at a time of said verifying operation and a second verifying transistor whose gate is controlled in accordance with a signal on said bit lines, whereby said first and second verifying transistors constitute a current path for inverting data in said data holding means when said verifying operation is completed. 
     
     
       12. The non-volatile semiconductor memory device according to claim 9, further comprising a first verifying transistor which conducts at a time of a first verifying operation, a second verifying transistor which conducts at a time of a second verifying operation, and a third verifying transistor whose gate is controlled in accordance with a signal on said bit lines, whereby said first and third verifying transistors constitute a first current path for inverting data in said data holding means when said first verifying operation is completed and said second and third verifying transistors constitute a second current path for inverting data in said data holding means when said second verifying operation is completed. 
     
     
       13. The non-volatile semiconductor memory device according to claim 5, wherein said memory cells are provided in a matrix form and a structural unit of said bistable data holding means and said first and second transfer control means is commonly connected to a plurality of bit lines. 
     
     
       14. The non-volatile semiconductor memory device according to claim 5 or 13, wherein said memory cells are provided in a matrix form and there are a plurality of structural units of said bistable data holding means and said first and second transfer control means, each structural unit renders said first transfer control means conductive and said second transfer control means non-conductive in read mode to simultaneously sense a plurality of bit line potentials, and after data of said bistable data holding means is entirely unchanged or only a part of said data is changed externally, said each structural unit renders said first transfer control means non-conductive and said second transfer control means conductive in write mode, thereby transferring contents of said data holding means onto said bit lines. 
     
     
       15. The non-volatile semiconductor memory device according to claim 14, wherein a first row of memory cells in said matrix is selected in read mode, and a second row of memory cells in said matrix is selected in write mode. 
     
     
       16. The non-volatile semiconductor memory device according to claim 15, further including means for previously erasing contents of said memory cells connected to said second row before said second row is selected. 
     
     
       17. A non-volatile semiconductor memory device comprising: memory cells having own threshold values as transistors for distinguishing conductiveness or nonconductiveness, for storing data corresponding to said threshold values;   a latch type sense amplifier having first and second latch nodes for latching complimentary signals, latching data of said memory cells at said first latch node as read data;   first data control means for using said read data as data to be written in said memory cells; and   second data control means for using data at said second latch node, which is inverted data of said read data, as data to be written in said memory cells.   
     
     
       18. The non-volatile semiconductor memory device according to claim 17, wherein said first data control means includes first verifying means for setting said data within a threshold value range corresponding to said data to be written. 
     
     
       19. The non-volatile semiconductor memory device according to claim 17, wherein said second data control means includes second verifying means for setting said data within a threshold value range corresponding to said data to be written. .Iadd. 
     
     
       20.  A nonvolatile semiconductor memory device comprising: a memory cell unit comprising a plurality of memory cells connected in series;   a bit line connected to said memory cell unit;   a latch circuit, having first and second nodes, for storing data;   a first transistor having a first end connected to ground and a second end, wherein a conductive state of said first transistor is controlled in accordance with a potential of said bit line;   a second transistor having a first end connected to said second node of said latch circuit and a second end connected to said second end of said first transistor, wherein a conductive state of said second transistor is controlled by a first timing signal; and   a third transistor having a first end connected to said first node of said latch circuit and a second end connected to said second end of said first transistor, wherein a conductive state of said third transistor is controlled by a second timing signal. .Iaddend..Iadd.21. A device according to claim 20, wherein said first node of said latch circuit is set to a high level and said second node of said latch circuit is set to be a low level after data stored in said latch circuit is written to a selected memory cell of said memory cell unit. .Iaddend..Iadd.22. A device according to claim 20, wherein said latch circuit comprises a flip-flop circuit including first and second inverter circuits, wherein an input terminal of said first inverter circuit is coupled to an output terminal of said second inverter circuit and an output terminal of said first inverter circuit is coupled to an input terminal of said second inverter circuit. .Iaddend..Iadd.23. A nonvolatile semiconductor memory device comprising:   a memory cell unit comprising a plurality of memory cells connected in series;   a bit line connected to said memory cell unit;   a latch circuit, having first and second nodes, for storing data;   a first transistor having a current path connected between said bit line and said first node of said latch circuit, wherein said first transistor supplies data stored in said latch circuit to a selected memory cell of said memory cell unit in accordance with a first timing signal supplied to a gate thereof;   a second transistor having a first end connected to ground and a second end, wherein a conductive state of said second transistor is controlled in accordance with a potential of said bit line;   a third transistor having a first end connected to said second node of said latch circuit and a second end connected to said second end of said second transistor, wherein a conductive state of said third transistor is controlled by a second timing signal; and   a fourth transistor having a first end connected to said first node of said latch circuit and a second end connected to said second end of said second transistor, wherein a conductive state of said fourth transistor is   
     
     
        controlled by a third timing signal. .Iaddend..Iadd.24.  A device according to claim 23, wherein said latch circuit comprises a flip-flop circuit including first and second inverter circuits, wherein an input terminal of said first inverter circuit is connected to an output terminal of said second inverter circuit and an output terminal of said first inverter circuit is connected to an input terminal of said second inverter circuit. .Iaddend..Iadd.25. A nonvolatile semiconductor memory device comprising: memory cell units, each memory cell unit comprising a plurality of memory cells connected in series;   bit lines connected to said memory cell units;   latch circuits for storing data, each latch circuit having first and second nodes and being coupled to a respective corresponding one of said bit lines;   first transistors, each first transistor having a first end connected to ground and a second end, wherein conductive states of said first transistors are controlled in accordance with a potential of a respective corresponding one of said bit lines;   second transistors, each second transistor having a first end connected to the second node of a respective corresponding one of said latch circuits and a second end connected to the second end of a respective corresponding one of said first transistors, wherein conductive states of said second transistors are controlled by a first timing signal; and   third transistors, each third transistor having a first end connected to the first node of a respective corresponding one of said latch circuits and a second end connected to a second end of a respective corresponding one of said first transistors, wherein conductive states of said third   
     
     
        transistors is controlled by a second timing signal. .Iaddend..Iadd.26.  A nonvolatile semiconductor memory device comprising: a memory cell unit comprising a plurality of memory cells connected in series;   a bit line connected to said memory cell unit;   a flip-flop circuit for storing data coupled to said bit line, said flip-flop circuit including first and second inverter circuits wherein an input terminal of said first inverter circuit is connected to an output terminal of said second inverter circuit and an output terminal of said first inverter circuit is connected to an input terminal of said second inverter circuit;   a first transistor having a first end connected to ground and a second end, wherein a conductive state of said first transistor is controlled in accordance with a potential of said bit line; and   second and third transistors having first ends commonly connected to the second end of said first transistor, a second end of said second transistor being connected to said output terminal of said first inverter circuit and a second end of said third transistor being connected to said output terminal of said second inverter circuit, wherein conductive states of said second and third transistors are controlled by respective first and second timing signals. .Iaddend.