Dual channel readback recovery system

Abstract

A dual channel readback recovery circuit includes a high resolution channel and a low resolution channel and a data latch. A logical filter in one or both channels rejects signals that are followed by other signals if they are spaced apart less than the rejection time interval allowed by the code used. Polarity qualifying logic rejects signals in the channel that are not matched in polarity.

What is claimed is: 
     
       1. A dual channel readback recovery system having a high resolution channel for receiving a read signal and producing high resolution pulse signals representative of digital information contained in said read signal, and having a low resolution channel for receiving said read signal and producing low resolution pulse signals representative of digital information contained in said read signal, said digital information being encoded in a predetermined code characterized in that pulse signals representative of said digital information are spaced at least a predetermined time interval apart, the improvement comprising: logical filter means in at least one of said channels for rejecting pulses spaced less than said time interval; and validation logic means responsive to unrejected high and low resolution pulse signals to recover said digital information. 
     
     
       2. Apparatus according to claim 1 wherein said logical filter means comprises monostable means responsive to edges of pulses recovered from said read signal to set to a first state, timer means responsive to said edges of said pulses for establishing a time period, said time period being restarted by each pulse edge, said monostable means being responsive to said timer means to reset to a second state upon expiration of said time period. 
     
     
       3. Apparatus according to claim 2 further including bistable means responsive to said monostable means to alter the state of said bistable means each time said monostable means resets to its second state. 
     
     
       4. Apparatus according to claim 1 wherein said pulse signals comprises first and second complementary pulse signals, said logical filter means comprising a first plurality of serially-connected gate means responsive to said first pulse signals and a second plurality of serially-connected gate means responsive to said second pulse signals, first collector gate means responsive to each gate means of said first plurality of gate means to set a first gate signal to a first logic level whenever any of said gate means of said first plurality of gate means responds to a pulse of a first polarity and to set said first gate signal to a second logic level whenever all of said gate means of said first plurality of gate means responds to a pulse of a second polarity, second collector gate means responsive to each gate means of said second plurality of gate means to set a second gate signal to a first logic level whenever any of said gate means of said second plurality of gate means responds to a pulse of a first polarity and to set said second gate signal to a second logic level whenever all of said gate means of said second plurality of gate means responds to a pulse of a second polarity; and latch means responsive to said first and second collector gate means to set a pulse whenever either of said first and second collector gate means sets its respective gate signal to said second logic level. 
     
     
       5. Apparatus according to claim 1 wherein said pulse signals comprises first and second complementary pulse signals, said logical filter means comprising: first and second strings of serially-connected logic gates responsive to said first and second pulse signals, respectively; first and second NOR gates having their inputs connected to the outputs of each logic gate of the respective first and second strings; and a latch connected to said first and second NOR gates. 
     
     
       6. Apparatus according to claim 1 wherein said unrejected high and low resolution pulse signals comprise complementary first and second high resolution pulse signals and complementary first and second low resolution pulse signals, respectively; said validation logic means comprising first and second bistable means each having clock and reset inputs, the reset inputs of said first and second bistable means being connected to receive said second and first low resolution pulse signals, respectively, and the clock inputs of said first and second bistable means being connected to receive said first and second high resolution pulse signals, respectively; and pulse forming means responsive to said first and second bistable means to produce a pulse signal representative of said digital information. 
     
     
       7. Apparatus according to claim 6 wherein said logical filter means comprises monostable means responsive to edges of pulses recovered from said read signal to set to a first state, timer means responsive to said edges of said pulses for establishing a time period, said time period being restarted by each pulse edge, said monostable means being responsive to said timer means to reset to a second state upon expiration of said time period. 
     
     
       8. Apparatus according to claim 7 further including bistable means responsive to said monostable means to alter the state of said bistable means each time said monostable means resets to its second state. 
     
     
       9. Apparatus according to claim 6 wherein said pulse signals comprises first and second complementary pulse signals, said logical filter means comprising a first plurality of serially-connected gate means responsive to said first pulse signals and a second plurality of serially-connected gate means responsive to said second pulse signals, first collector gate means responsive to each gate means of said first plurality of gate means to set a first gate signal to a first logic level whenever any of said gate means of said first plurality of gate means responds to a pulse of a first polarity and to set said first gate signal to a second logic level whenever all of said gate means of said first plurality of gate means responds to a pulse of a second polarity, second collector gate means responsive to each gate means of said second plurality of gate means to set a second gate signal to a first logic level whenever any of said gate means of said second plurality of gate means responds to a pulse of a first polarity and to set said second gate signal to a second logic level whenever all of said gate means of said second plurality of gate means responds to a pulse of a second polarity; and latch means responsive to said first and second collector gate means to set a pulse whenever either of said first and second collector gate means sets its respective gate signal to said second logic level. 
     
     
       10. Apparatus according to claim 6 wherein said pulse signals comprises first and second complementary pulse signals, said logical filter means comprising: first and second strings of serially-connected logic gates responsive to said first and second pulse signals, respectively; first and second NOR gates having their inputs connected to the outputs of each logic gate of the respective first and second strings; and a latch connected to said first and second NOR gates. 
     
     
       11. Apparatus according to claim 1 wherein said unrejected high and low resolution pulse signals comprise complementary first and second high resolution pulse signals and first and second low resolution pulse signals, respectively; said validation logic means comprises first and second D-flip-flops having their reset inputs connected to receive said second and first low resolution pulse signals, respectively, and having their clock inputs connected to receive said first and second high resolution pulse signals, respectively; and an OR gate having its inputs connected to the output of said first and second D-flip-flops; and a positive edge pulse former connected to the output of said OR gate. 
     
     
       12. Apparatus according to claim 1 wherein said validation logic means comprises bistable means having a clock input connected to receive said unrejected high resolution pulse signals and a data input connected to receive said unrejected low resolution pulse signals, and pulse former means responsive to setting and resetting of said bistable means to produce a pulse signal representative of said digital information. 
     
     
       13. Apparatus according to claim 12 wherein said logical filter means is in said low resolution channel. 
     
     
       14. Apparatus according to claim 1 further including control means for controlling signal delays in said logical filter means, said control means comprising ring oscillator means responsive to a system clock signal. 
     
     
       15. Apparatus according to claim 14 further including variable delay means in one of said channels responsive to said control means for synchronizing the propagation time of the two channels. 
     
     
       16. Apparatus according to claim 14 wherein said control means further includes phase compare means responsive to said system clock signal and to said ring oscillator means for determining phase/frequency difference, pump means responsive to said phase compare means providing a signal representative of said phase/frequency difference, said oscillator means being responsive to said pump means to provide a signal phase and frequency locked to said clock signal. .Iadd. 
     
     
       17.  A readback recovery system having a high resolution channel for receiving a read signal and producing high resolution pulse signals representative of digital information contained in the read signal, the digital information being encoded in a predetermined code characterized in that pulse signals representative of the digital information are spaced at least a predetermined time interval apart, the improvement comprising; logical filter means for rejecting pulses spaced less than the predetermined time interval;   control means for controlling signal delays in the logical filter means, the control means comprising ring oscillator means responsive to a system clock signal; and   means for recovering the digital information encoded in the high resolution pulse signals which are not rejected by the logical filter means. .Iaddend..Iadd.   
     
     
       18.  The apparatus of claim 17 wherein the control means further includes: phase compare means, responsive to the system clock signal and to the ring oscillator means for determining phase/frequency difference; and   pump means responsive to the phase compare means providing a signal representative of the phase/frequency different, the ring oscillator means being responsive to the pump means in order to provide a signal phase and frequency locked to the system clock signal. .Iaddend..Iadd.19. The apparatus of claim 17 further comprising:   a low resolution channel for receiving the read signal and producing low resolution pulse signals representative of digital information contained in the read signal. .Iaddend..Iadd.20. The apparatus of claim 19 wherein the logical filter means is in both the high resolution channel and the low resolution channel. .Iaddend..Iadd.21. The apparatus of claim 19 further including:   variable delay means in one of the channels responsive to the control means for synchronizing a propagation time of the two channels. .Iaddend..Iadd.22. A readback recovery system having a high resolution channel for receiving a read signal and producing high resolution pulse signals representative of digital information contained in said read signal, said digital information being encoded in a predetermined code characterized in that pulse signals representative of said digital information are spaced at least a predetermined time interval apart, the improvement comprising:   logical filter means in the high resolution channel for rejecting pulses spaced less than said time interval;   control means for controlling signal delays in the logical filter means, the control means being responsive to a system clock signal; and   means responsive to unrejected high resolution pulse signals to recover   
     
     
        said digital information. .Iaddend..Iadd.23.  Apparatus according to claim 22, said control means comprises ring oscillator means responsive to the system clock signal. .Iaddend..Iadd.24. Apparatus according to claim 23 wherein said control means further includes phase compare means responsive to said system clock signal and to said ring oscillator means for determining phase/frequency difference, pump means responsive to said phase compare means providing a signal representative of said phase/frequency difference, said oscillator means being responsive to said pump means to provide a signal phase and frequency locked to said clock signal. .Iaddend..Iadd.25. A readback recovery system having a first channel for receiving a read signal and producing first pulse signals representative of digital information contained in said read signal, said digital information being encoded in a predetermined code characterized in that pulse signals representative of said digital information are spaced at least a predetermined time interval apart, the improvement comprising: logical filter means in the first channel for rejecting pulses spaced less than said time interval;   control means for controlling signal delays in the logical filter means, the control means being responsive to a system clock signal; and   validation logic means responsive to unrejected first pulse signals and at least one other signal to recover said digital information. .Iaddend..Iadd.26. Apparatus according to claim 25 wherein said control means comprises ring oscillator means responsive to the system clock signal. .Iaddend..Iadd.27. Apparatus according to claim 26 wherein said control means further includes phase compare means responsive to said system clock signal and to said ring oscillator means for determining phase/frequency difference, pump means responsive to said phase compare means providing a signal representative of said phase/frequency difference, said oscillator means being responsive to said pump means to provide a signal phase and frequency locked to said clock signal. .Iaddend..Iadd.28. For use in reading magnetic recording media, a high resolution data recovery system having a high resolution channel for receiving a read signal and producing high resolution signals representative of digital information contained in the read signal, the digital information being encoded in a predetermined code characterized in that pulse signals representative of the digital information are spaced at least a predetermined time interval apart, the improvement comprising:   a logical filter having variable slave delay elements in the high resolution channel for rejecting pulses spaced less than the predetermined time interval apart;   a controller for controlling the variable slave delay elements to synchronize propagation time through the high resolution channel to a period of a system clock signals; and   validation logic responsive to unrejected high resolution pulse signals and at least one other signal to recover the digital information. .Iaddend..Iadd.29. The apparatus according to claim 28 wherein the logical filter comprises:   a monostable apparatus responsive to edges of pulses recovered from the read signal to be set to a first state; and   a timer responsive to the edges of the pulses for establishing a time period, the time period being restarted by each pulse edge and where the monostable apparatus is responsive to the timer and is reset to a second   
     
     
        state upon expiration of the time period. .Iaddend..Iadd.30.  The apparatus of claim 29 and further comprising: a bi-stable apparatus responsive to the monostable apparatus, the bi-stable apparatus having a state which is altered each time the monostable apparatus resets to its second state. .Iaddend..Iadd.31. The apparatus of claim 28 wherein the high resolution signals comprise first and second complementary pulse signals. .Iaddend..Iadd.32. The apparatus according to claim 31 wherein the logical filter further comprises:   a first plurality of serially-connected gates responsive to the first pulse signals;   a second plurality of serially-connected gates responsive to the second pulse signals;   first collector gates responsive to each gate of the first plurality of gates to set a first gate signal to a first logic level when any of the gates of the first plurality of gates responds to a pulse of the first polarity and to set the first gate signal to a second logical level whenever all of the gates of the first plurality of gates responds to a pulse of a second polarity;   second collector gates responsive to each gates of the second plurality of gates to set a second gate signal to a first logic level whenever any of the gates of the second plurality of gates responds to a pulse of a first polarity and to set the second gate signal to a second logic level whenever all of the gates of the second plurality of gates responds to a pulse of a second polarity; and   a latch responsive to the first and second collector gates to set a pulse whenever either of the first and second collector gates sets its   
     
     
        respective gate signal to the second logic level. .Iaddend..Iadd.33.  The apparatus of claim 31 wherein and the logical filter comprises: first and second strings of serially-connected logic gates responsive to the first and second pulse signals, respectively;   first and second NOR gates having their inputs connected to the outputs of each logic gate of the responsive first and second strings; and   a latch connected to the first and second NOR gates. .Iaddend..Iadd.34. The apparatus of claim 28 and further comprising:   a low resolution channel for receiving the signal and producing low resolution signals representative of digital information contained in the read signal where the logical filter is in at least the high or low resolution channels. .Iaddend..Iadd.35. The apparatus of claim 34 wherein the validation logic is responsive to unrejected high and low resolution pulse signals to recover the digital information. .Iaddend..Iadd.36. The apparatus according to claim 35 wherein the unrejected high and low resolution pulse signals comprise complementary first and second high resolution pulse signals and complementary first and second low resolution pulse signals, respectively. .Iaddend..Iadd.37. The apparatus of claim 36 wherein the validation logic comprises:   first and second bi-stable devices each having clock and reset inputs, the reset inputs of the first and second bi-stable devices being connected to receive the second and first low resolution pulse signals, respectively, and the clock inputs being connected to receive the first and second high resolution pulse signals, respectively; and   a pulse former responsive to the first and second bi-stable to produce a pulse signal representative of the digital information.   
     
     
        .Iaddend..Iadd.     The apparatus of claim 37 wherein the logical filter comprises: a monostable device responsive to edges of pulses recovered from the read signal to set a first state; and   a timer responsive to the edges of the pulses for establishing a time period, the time period being restarted by each pulse edge and the monostable device being responsive to the timer to reset a second state upon expiration of the time period. .Iaddend..Iadd.39. The apparatus of claim 38 and further comprising:   a third bi-stable device responsive to the monostable device to alter the state of the third bi-stable device each time the monostable device reset to its second state. .Iaddend..Iadd.40. The apparatus of claim 37 wherein and the logical filter comprises:   a first plurality of serially-connected gates responsive to the first pulse signals;   a second plurality of serially-connected gates responsive to the second pulse signals;   first collector gates responsive to each gate of the first plurality of gates to set a first gate signal to a first logic level whenever any of the gates of the first plurality of gates responds to a pulse of a first polarity and to set the first gate signal to a second level whenever all of the gates of the first plurality of gates responds to a pulse of a second polarity;   second collector gates responsive to each gate of the second plurality of gates to set a second gate signal to a first logic level whenever any of the gates of the second plurality of gates responds to a pulse of a first polarity and to set the second gate signal to a second logic level whenever all of the gates of the second plurality of gates responds to a pulse of a second polarity; and   a latch responsive to the first and second oscillator gates to set a pulse whenever either of the first and second collector gates sets its   
     
     
        respective gate signal to the second logic level. .Iaddend..Iadd.41.  The apparatus of claim 37 wherein the logical filter comprises: first and second string of serially-connected logic gates responsive to the first and second pulse signals, respectively;   first and second NOR gates having their inputs connected to the outputs of each logic gate of the respective first and second strings; and   a latch connected to the first and second NOR gates. .Iaddend..Iadd.42. The apparatus of claim 36 wherein the validation logic comprises:   first and second D-flip-flop having their reset inputs connected to receive the second and first low resolution pulse signals, respectively, and having their clock inputs connected to receive the first and second high resolution pulse signals, respectively;   an OR gate having its inputs connected to the output of the first and second D-flip-flops; and   a positive edge pulse former connected to the output of the OR gate. .Iaddend..Iadd.43. The apparatus of claim 35 wherein the validation logic comprises:   a bi-stable device having a clock input connected to receive the unrejected high resolution pulse signals and a data input connected to receive the unrejected low resolution pulse signals; and   a pulse former responsive to setting and resetting of the bi-stable device to produce a signal representative of the digital information. .Iaddend..Iadd.44. The apparatus of claim 34 wherein the controller comprises:   a ring oscillator responsive to the system clock signal.   
     
     
        .Iaddend..Iadd.     The apparatus of claim 44 and further comprising: a variable delay apparatus in one of the channels responsive to the controller for synchronizing the propagation time of the two channels. .Iaddend..Iadd.46. The apparatus of claim 44 wherein the controller further comprises:   a phase compare device responsive to the system clock signal and to the ring oscillator for determining phase/frequency difference; and   a pump responsive to the phase compare device providing a signal representative of the phase/frequency difference, the ring oscillator being responsive to the pump to provide a signal phase and frequency locked to the system clock signal. .Iaddend.