Data processor and data processing system and method for accessing a dynamic type memory using an address multiplexing system

Abstract

A microprocessor has a register in which attributive data corresponding to a memory to be coupled to the microprocessor is written, and a control circuit which controls address signals to be supplied to the memory in accordance with the attributive data. The attributive data is composed of range data for discriminating ranges of address data supplied to an address bus, system data indicative of addressing systems of the memories corresponding to the respective address ranges, and bit number data indicative of numbers of address bits of the memories. Thus, in a case where the memory to be accessed is of an address multiplexing system as in a dynamic RAM, the address data of the address bus is divided into row address data and column address data, which are then supplied to the memory in time division.

I claim: 
     
       1. A .[.microprocessor.]. .Iadd.processor .Iaddend.formed on a single semiconductor substrate to be externally coupled to an external memory device, said .[.microprocessor.]. .Iadd.processor .Iaddend.comprising: .[.a CPU;.].   an address bus .[.coupled to said CPU.]. to which an address signal including a plurality of bits is applied, said address signal defining an address in said external memory device;   a data bus .[.coupled to said CPU for inputting and outputting.]. .Iadd.to which .Iaddend.data .Iadd.is applied.Iaddend.;   .[.external data terminals coupled to said data bus;   external address terminals.]. .Iadd.an address switching device .Iaddend.coupled to said address bus .[.via address switching means.].;   .[.first register means for storing address data identifying a boundary between a first address space and a second address space of said external memory device to be coupled to said external data terminals and said external address terminals of said microprocessor, wherein said external memory device includes a first memory having said first address space defining a range of addresses assigned thereto and a second memory having said second address and defining a range of addresses assigned thereto;.].   .[.second.]. .Iadd.a .Iaddend.register.Iadd., coupled to said data bus, .Iaddend..[.means.]. for storing attributive data .[.including first means for storing attributive data.]. corresponding to an attribute of said .[.first memory.]. .Iadd.external memory device, said attributive data being stored in said register via said data bus; .Iaddend.and   .[.second means for storing attributive data corresponding to an attribute of said second memory;   comparator means coupled to said first register means and said address bus for comparing an address signal of a plurality of bits on said address bus to said address data stored in said first register and for outputting a signal indicating whether said address signal on said address bus designates an address within the first address space;   selecting means coupled to said comparator means and said second register means and responsive to an output of said comparator means for selecting either said attributive data stored in said first means or said attributive data stored in said second means of said second register means and outputting said selected attributive data; and.].   .[.control means.]. .Iadd.a controller, .Iaddend.coupled to .[.said selecting means and.]. said address switching .[.means and responsive.]. .Iadd.device, for controlling, in response .Iaddend.to said .[.selected.]. attributive data.Iadd., .Iaddend..[.for controlling.]. said address switching .[.means so.]. .Iadd.device such .Iaddend.that said address switching .[.mean.]. .Iadd.device .Iaddend.delivers said address signal on said address bus .[.to said external address terminals.]. according to an address multiplexing system.Iadd., wherein .Iaddend..[.according to which.]. a first part of said plurality of bits of said address signal and a second part of said plurality of bits of said address signal are delivered to said .[.external address terminals.]. .Iadd.external memory device.Iaddend., individually.[., when said selected attributive data indicates that said external memory device should be addressed according to said address multiplexing system.].. .[.2. A microprocessor according to claim 1, wherein said first register means is coupled to said data bus..]..[.3. A microprocessor according to claim 2, wherein said second   
     
     
        register means is coupled to said data bus..].4. A .[.microprocessor.]. .Iadd.processor .Iaddend.according to claim 1, wherein said address switching .[.means.]. .Iadd.device .Iaddend.includes .[.means for latching.]. .Iadd.a latch which latches .Iaddend.one of said first and second parts of said plurality .Iadd.of .Iaddend.bits of said address 
     
     
        signal on said address bus. 5. A .[.microprocessor.]. .Iadd.processor .Iaddend.according to claim 1, wherein said first and second parts of said plurality of bits of said address signal corresponds to first and second halves of said plurality of bits of said address signal, and wherein said first and second halves of said plurality of bits of said address signal are both delivered to same terminals in .[.said.]. external address terminals .[.when said selected attributive data indicates that said external memory device should be addressed according to the address 
     
     
        multiplexing system.]. .Iadd.coupled to said address bus.Iaddend.. 6. A .[.microprocessor.]. .Iadd.processor .Iaddend.according to claim 1, wherein said address .[.switching means allows said address signals to pass therethrough to be supplied to said address bus at said external address terminals when said selected attributive data indicates that said external memory device is not to be addressed according to said address multiplexing system.]. .Iadd.bus is coupled to a CPU and said data bus is coupled to said CPU and wherein said CPU is formed on said single 
     
     
        semiconductor substrate.Iaddend.. 7. A .[.microprocessor.]. .Iadd.processor .Iaddend.according to claim 1, further comprising: .Iadd.external data terminals; and .Iaddend.   .Iadd.a.Iaddend. data buffer coupled between said data bus and said   
     
     
        external data terminals. 8. A .[.microcomputer.]. .Iadd.processor .Iaddend.according to claim 1, further comprising: a refresh .[.address formation means coupled to said address switching means.]. .Iadd.circuit .Iaddend.for providing .[.refresh address data and.]. a refresh timing signal for .[.the.]. .Iadd.said .Iaddend.external memory device .[.which is to be addressed according to said address multiplexing system;   wherein said control means controls said address witching means in response to said refresh timing signal so that said address switching means provides said refresh address data to said external address terminal.]..   
     
     
           A .[.microcomputer.]. .Iadd.processor .Iaddend.according to claim 1, wherein said first and second parts of said plurality of bits of said address signal correspond to row and column address signals of said external memory device, respectively, wherein said .[.control means.]. .Iadd.controller .Iaddend.includes .[.means for providing.]. .Iadd.a circuit which provides .Iaddend.a row address strobe signal and a column address strobe signal, said row address strobe signal being provided in synchronism with an output of said row address signal, said column address strobe signal being provided in synchronism with an output of said column address signal, .Iadd.and .Iaddend.wherein said .[.microprocessor.]. .Iadd.processor .Iaddend.further comprises: first and second terminals at which said row and .[.second.]. .Iadd.column   
     
     
        .Iaddend.address strobe signals are received, respectively. 10. A .[.microcomputer.]. .Iadd.processor .Iaddend.according to claim 1, wherein said attributive data stored in said .[.first and second means each.]. .Iadd.register .Iaddend.includes information indicating a memory capacity of .[.the corresponding memory in the.]. .Iadd.said .Iaddend.external memory device, and wherein said .[.control means.]. .Iadd.controller .Iaddend.controls said address switching .[.means.]. .Iadd.device .Iaddend.in response to the information regarding the memory capacity in the .[.selected.]. attributive data .Iadd.such that a bit number of respective first and second parts of said address signal to be applied to 
     
     
        said external memory device is based on said information.Iaddend.. 11. A microcomputer system comprising: an external memory device including at least one dynamic RAM of a first memory part and a second memory part other than said dynamic RAM, said external memory device having a first address space defining a range of addresses assigned to said at least one dynamic RAM of said first memory part and a second address space defining a range of addresses assigned to said second memory part; and   a microprocessor coupled to said external memory device for accessing said external memory device said microprocessor including.Iadd.: .Iaddend.   a CPU coupled to an address bus and to a data bus,   address switching means coupled between said address bus and a plurality of external address terminals for switching said address bus between said plurality of external address terminals,   first register means for storing address data identifying a boundary between said first and second address space,   second register means for storing addressing system data including first means for storing addressing system data of said first memory part and second means for storing addressing system data of said second memory part,   comparator means coupled to said address bus and said first register means and responsive to an address signal of a plurality of bits supplied from said CPU to said address bus for comparing said address signal with said address data stored in said first register means and for outputting a signal indicating whether said address signal designates an address within said first address space of said first memory part,   selecting means coupled to said comparator means and said second register .Iadd.means .Iaddend.and responsive to an output of said comparator means for selecting addressing system data of said first memory part when said output of said comparator means indicates that said address signal designates an address within said first address space of said first memory part and control means.Iadd., .Iaddend.coupled to said selecting means and said address switching means.Iadd., .Iaddend..[.and responsive.]. .Iadd.for controlling, in response .Iaddend.to said selected .[.address.]. .Iadd.addressing .Iaddend.system data.Iadd., .Iaddend..[.for controlling.]. said address switching means .[.to deliver.]. .Iadd.such that said address switching means delivers .Iaddend.said address signal .[.to said external address terminals.]. .Iadd.on said address bus .Iaddend.according to an address multiplexing system.Iadd., wherein .Iaddend..[.according to which.]. a first part of said plurality of bits of said address signal and a second part of said plurality of bits of said address signal are delivered to said external address terminals,   
     
     
        individually. 12. A microcomputer system according to claim 11, wherein 
     
     
        said first register means has inputs coupled to said data bus. 13. A microcomputer system according to claim 11, wherein said second register 
     
     
        means has inputs coupled to said data bus. 14. A microcomputer system according to claim 11, wherein said second memory part includes a static 
     
     
        type RAM. 15. A microcomputer system according to claim 11, wherein said 
     
     
        second memory part includes a ROM. 16. A microcomputer system according to claim 11, further comprising: a refresh address formation means coupled to said address switching means for forming refresh address data for the dynamic RAM of said first memory part and for providing a refresh timing signal to .[.the.]. .Iadd.said at least one .Iaddend.dynamic RAM of said first memory part;   wherein said control means controls said address switching means in response to said refresh timing signal so that said address switching means provides said refresh address data to said external address   
     
     
        terminals. 17. A microprocessor according to claim 11, further comprising: wherein said first and second parts of said plurality of bits of said address signal correspond to row and column address signals of said at least one dynamic RAM, respectively;   wherein said control means includes means for providing a row address strobe signal and a column address strobe signal to said at least one dynamic RAM;   wherein said row address strobe signal is provided in synchronism with an output of said row address signal; and   wherein said column address strobe signal is provided in synchronism with   
     
     
        an output of said column address signal. 18. A microcomputer system of claim 11, wherein said first and second parts of said plurality of bits of said address signal correspond to first and second halves of said plurality of bits of said address signal, and wherein said first and second halves of said plurality of bits of said address .[.signals.]. .Iadd.signal .Iaddend.are both delivered to same terminals in said external address terminals when said selected .[.attributive.]. .Iadd.addressing system .Iaddend.data indicates that said external memory device should be addressed according to the address multiplexing system. 
     
     
          . The microcomputer system of claim 11, wherein said address switching means allows said address .[.signals.]. .Iadd.signal .Iaddend.to pass therethrough to be supplied to said address .[.but.]. .Iadd.bus .Iaddend.at said external address terminals when said selected .[.attributive.]. .Iadd.addressing system .Iaddend.data indicates that the external memory device is not to be addressed according to said address 
     
     
        multiplexing system. 20. The microcomputer system of claim 11, wherein said address switching means includes means for latching one of said first and second parts of said plurality of bits of said address signal on said 
     
     
        address bus. 21. The microcomputer system according to claim 11, wherein .[.said attributive data stored in.]. said first and second .Iadd.register .Iaddend.means each .[.includes.]. .Iadd.further stores .Iaddend.information indicating a memory capacity of the corresponding memory in the external memory device, and wherein said control means controls said address switching means in response to the information regarding the memory capacity .Iadd.stored .Iaddend.in the selected .[.attributive data.]. .Iadd.one of said first and second register means.Iaddend.. .Iadd.22. A processor according to claim 10, wherein said 
     
     
        register has a plurality of bits for the information. .Iaddend..Iadd.23. A processor for accessing an address space including first addresses assigned to a dynamic type memory and second addresses assigned to a memory other than a dynamic type memory, said processor comprising: an address bus to which an address signal of a plurality of bits is applied, said address signal defining an address in the address space;   a data bus to which data is applied;   external address terminals;   an address switching device coupled between the address bus and the external address terminals;   a register, coupled to said data bus for storing attributive data corresponding to a memory capacity of the dynamic memory, wherein said attributive data is written to said register via said data bus; and   a controller, coupled to the address switching device, for controlling said address switching device such that said address switching device delivers said address signal on said address bus according to an address multiplexing system, wherein a first part of said plurality of bits of said address signal and a second part of said plurality of bits of said address signal are delivered to said external address terminals in time division manner when said processor accesses an address in said first addresses,   wherein said controller, responsive to said attributive data, controls said address switching device so that a bit number of respective first and second parts of said plurality of bits of said address signal is determined based on said attributive data stored in said register. .Iaddend..Iadd.24. A processor according to claim 23, wherein said first and second parts of said plurality of bits of said address signal correspond to row and column address signals of said dynamic type memory, respectively. .Iaddend..Iadd.25. A processor according to claim 24, wherein said controller includes a circuit which provides a row address strobe signal and a column address strobe signal, and   wherein said processor further comprises:   first and second external terminals coupled to receive said row and column address strobe signals, respectively, to output said row and column address strobe signals to outside of said processor. .Iaddend..Iadd.26. A processor according to claim 23, wherein said attributive data is written by a CPU to said register via said data bus. .Iaddend..Iadd.27. A processor according to claim 26, wherein said CPU is provided on a same semiconductor substrate as said processor, and wherein said CPU is coupled to said address and data buses. .Iaddend..Iadd.28. A processor according to claim 23, wherein said register has a plurality of bits for said attributive data. .Iaddend..Iadd.29. A processor according to claim 23, wherein said address switching device allows said address signal on said address bus to pass therethrough at said external address terminals when said processor accesses an address in the second addresses in an external   
     
     
        address space. .Iaddend..Iadd.30.  A processor which is formed on a single semiconductor substrate, and which can be externally coupled to a memory, said processor comprising: an address bus to which an address signal for the memory is supplied;   a data bus to which data is supplied;   a register including a first bit in which data corresponding to a kind of the memory is to be written and a second bit in which data corresponding to a capacity of the memory is to be written;   an address switching circuit coupled to said address bus; and   a control circuit which controls said address switching circuit,   wherein said control circuit includes a circuit which discriminates whether the memory is accessed according to an address multiplexing system based on data stored in said first bit of said register;   wherein said control circuit controls said address switching circuit such that said address switching circuit supplies first and second parts of said address signal on said address bus to the memory in time division manner when said data stored in said first bit of said register indicates that the memory is to be accessed according to said address multiplexing system,   wherein said control circuit further controls said address switching circuit such that said address switching circuit determines a bit number of respective first and second parts of said address signal based on data stored in said second bit of said resister when said data stored in said first bit of said register indicates that the memory is to be accessed according to said address multiplexing system, and   wherein said control circuit controls said address switching circuit such that said address switching circuit supplies the first and second parts of said address signal to the memory, simultaneously, when said data stored in said first bit of said resister indicates that the memory is not to be accessed according to said address multiplexing system. .Iaddend..Iadd.31. A processor according to claim 29, wherein said first and second parts of said address signal corresponds to row and column address signals, respectively. .Iaddend..Iadd.32. A processor according to claim 31, wherein said controller includes a circuit which provides a row address strobe signal and a column address strobe signal, and   wherein said processor further comprises:   first and second external terminals which are coupled to receive said row and column address strobe signals, respectively and which output said row and column address strobe signals to outside of said processor. .Iaddend..Iadd.33. A processor according to claim 32, further comprising:   a CPU coupled to said address and data buses,   wherein said data stored in said first bit of said register and said data stored in said second bit of said register are written by said CPU to said   
     
     
        register via said data bus. .Iaddend..Iadd.34.  A method of accessing a dynamic type memory by a processor, said method comprising the steps of: writing data corresponding to a memory capacity of a dynamic type memory to be used in a data processing system to a register via a data bus, wherein said register and said data bus are included in said processor, and wherein said register is coupled to said data bus;   after said writing step, outputting controlled row and column address signals whose bit number is controlled based on said data written in said register from said processor to the dynamic type memory in time division manner; and   accessing said dynamic type memory with said controlled row and column address signals. .Iaddend..Iadd.35. A method according to claim 34, wherein said outputting step is preformed by an address switching circuit responding to data written in the register, said address switching circuit being included in the processor. .Iaddend..Iadd.36. A method according to claim 34, wherein said writing step is performed by a CPU.   
     
     
        .Iaddend..Iadd. 7.  A method according to claim 36, further comprising the step of: before said writing step, reading out data from a read only memory by said CPU executing a data set program stored in the read only memory. .Iaddend..Iadd.38. A method according to claim 37, wherein said CPU is included in the processor which is formed on a semiconductor substrate. .Iaddend..Iadd.39. A method of organizing a function of a data processor included in a data processing system, said processor accesses a dynamic type random access memory using an address multiplexing system, said method comprising the steps of:   resetting a first bit of a register in the data processor to a first state in order to access a read only memory using a system other than the address multiplexing system;   reading out first data corresponding to an address access system of the dynamic type random access memory and second data corresponding to a memory capacity of the dynamic type random access memory from the read only memory to a data bus in the data processor;   setting a function of the data processor for outputting row and column address signals in time division manner to the dynamic type random access memory by writing the first data on the data bus to a first bit of the register via the data bus;   setting the function of the data processor to set a bit number of the respective row and column address signals to be supplied to the dynamic type random access memory based on the second data by writing the second data on the data bus to one or more second bits of the register via the data bus. .Iaddend..Iadd.40. A method according to claim 39, wherein said reading out step is performed by a CPU. .Iaddend..Iadd.41. A method according to claim 40, wherein said setting steps are performed by the CPU. .Iaddend..Iadd.42. A method according to claim 41, wherein the read only memory stores the first data, the second data and a program including a data set program, and wherein said setting steps are performed by the CPU executing the data set program in the program. .Iaddend..Iadd.43. A method according to claim 42, wherein the processor is formed on a semiconductor substrate. .Iaddend..Iadd.44. A method according to claim 43, wherein the CPU is provided on the semiconductor substrate. .Iaddend.